Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0 V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

Study of asymmetrical effects of silicon submicron transistors

We studied the asymmetrical effect of submicron channel length NMOS silicon transistors. The threshold voltage of transistor was determined by transconductance (g_m) extraction method and constant-current (CC) method. The effective channel length (L_eff) was determined by ‘shift and ratio’ methods. The short channel and reverse short channel effect were observed from the threshold voltage (V_to) versus channel width (W) curve. The I-V curves were not shown significant asymmetry of drain and source. The results showed that the asymmetry of drain and source increased with reducing the channel length. The standard deviation of threshold voltage and effective channel length were increased with decreasing channel length.     

Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors

The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the off-current in the metal-oxide-semiconductor transistors. This paper demonstrates that the halo implant from the drain side can cross-over to the source side and vice versa for the look-ahead transistor test structures (transistor test structures with gate length smaller than that of the target transistor). The phenomenon of the cross-over of halo implant is more readily observed in PMOS transistors compared to NMOS transistors because for the same mask gate length, the effective channel length of PMOS transistor tends to be smaller than that of NMOS transistor. The advantage of the cross-over of halo implants can be understood as follows. Since the hole mobility is smaller than the electron mobility in silicon, PMOS transistor tends to have smaller on-current (I_on) than NMOS transistor. The on-current can be increased by using PMOS transistor with smaller mask gate length compared to the NMOS transistor. However, this approach will make the PMOS transistor very sensitive to the statistical variation in the gate electrode length during manufacturing. By making use of the above reported phenomenon, PMOS transistor can be made shorter without running into manufacturing control problem, resulting in bigger I_on but the penalty is that the I_off will become significantly higher.     

Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

A new MNOS memory element—the tunnel diode

MNOS (Metal-Nitride-Oxide-Silicon) memory devices commercially available today consist of transistor arrays where each device represents a memory bit. Typical devices have densities greater than 8 K bits and are generally manufactured on epitaxial based processes for isolation. The state of each bit is determined by its threshold voltage and is sensed by interpreting if the transistor is in the “off” or “on” condition. A new MNOS memory element is described where detection of junction tunnelling current is used as the sense mechanism. Substrate forms the “third” terminal and the element has the possibility of being the basis of a dense array. The technique can be developed in p or n channel and can be used as an add-on to volatile random access memories.     

Inversion charge transistor (ICT) for better threshold control in small dimensions

Data are presented to show that threshold voltage is less dependent on channel length for an inversion charge transistor than for a regular IGFET. Thus, for an acceptable threshold tolerance, an inversion charge transistor can be operated with a smaller channel length than an IGFET.     

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices

In this paper, we investigate the threshold voltage fluctuation for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) and silicon-on-insulator (SOI) devices. The threshold voltage fluctuation comes from random dopant and short channel effects. The random-dopant-induced fluctuation is due to the random nature of ion implantation. The gate-length deviation and the line-edge roughness are mainly resulted from the short-channel effect. For the SOI devices, we should also consider the body thickness variation. In our investigation, the metal gate with high-κ material MOSFET is a good choice to reduce fluctuation of threshold voltage when comparing to the poly gate MOSFET and thin-body SOI devices.     

Model for the channel-implanted enhancement-mode IGFET

A simple dc four-terminal "channel-implanted model" is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are shown to agree to within 25 mV across a 15-V range of VSB. Modeled and measured transistor currents agree to within 5 percent across a 10-V range of VSBfor medium- to long-channel length transistors (L_{drawn} ge 2.5µm). The channel impurity profile is approximated as a constant effective impurity concentration NAEextending from the semiconductor surface through the implanted region to an effective implant depth XDE("box" profile approximation). At depths greater than XDE, the bulk substrate impurity concentration is approximated as a constant, NA. The model is composed of two threshold voltage equations, three drain current equations, two saturation voltage equations, and two boundary equations. All first-order model equations and all of their first derivatives are continuous at all boundaries. The model's continuity and its accuracy make it useful for circuit simulation. Extrapolation of channel concentration profile parameters NAE, XDE, and NAfrom measured threshold voltages yields information on implant profile and on field-implant impurity encroachment into the transistor channel.     

Numerical study of the effect of the doping profile on the threshold voltage of narrow-channel MOS transistor

A two-dimensional MOS process and device simulator, called IMPEDANCE, is used to study the influence of various doping profiles of stopper and channel implantations on the threshold voltage of narrow-channel MOS transistor (made with LOCOS isolation technology). For enhancement-mode transistors without channel implantation the lateral spread of the stopper implantation is the main factor for the threshold voltage increase with decreasing channel width. However the increase of the channel implantation dose reduces the dependence of the threshold voltage on the width especially at higher ion energies. In case of depletion-mode transistors the dependence of the threshold voltage on width is stronger owing to: (1) the existence of a lateral p-n junction between the channel and the stopper region and (2) the weaker gate control of the channel carriers.     

D’yakonov-Shur instability in a ballistic field-effect transistor with a spatially nonuniform channel

The instability of a two-dimensional electronic liquid in the channel of a ballistic field-effect transistor is analyzed by investigating the energy balance. A criterion of instability is found for arbitrary boundary conditions. Using energy-balance analysis we propose a device with a high instability growth rate. The transistor possesses a spatially nonuniform channel and is analogous to a divergent channel in classical hydrodynamics. Our computed growth rate and threshold of the instability for this device agree with the computational data. Fiz. Tekh. Poluprovodn. 33, 619–628 (May 1999)     

A new method to determine MOSFET channel length

A new method is proposed to electrically determine MOS transistor channel length with both accuracy and convenience. Based on the linear region relationship between effective channel length Leffand channel resistance Rchanof an MOS transistor, this method determines Leffby applying relatively large but constant gate voltage to eliminate threshold voltage determination and takes into account external resistance. Comparison of this method with SEM measurement shows very good agreement (within ±0.1 µm resolution limit of our SEM technique).     

SOI铁电负电容晶体管亚阈值特性研究

随着微电子技术进入纳米领域,功耗成为制约技术发展的主要因素,因此,低功耗器件成为半导体器件领域的研究热点。负电容场效应晶体管基于铁电材料的负电容效应可有效地降低器件的亚阈值摆幅,从而降低器件的功耗。该文设计了一种基于绝缘体上硅(SOI)结构的铁电负电容场效应晶体管,利用TCAD Sentaurus仿真工具对负电容晶体管进行仿真研究,得到了亚阈值摆幅为30.931 mV/dec的负电容场效应晶体管的器件结构和参数。最后仿真研究了铁电层厚度、等效栅氧化层厚度对负电容场效应晶体管亚阈值特性的影响。     

Modelling for the current-voltage characteristics of SOI submicrometre gate controlled hybrid transistors

An improved physical model for the collector current in the SOI submicrometre gate-controlled hybrid transistor (GCHT) is presented in this paper, with the bias-dependent dynamic threshold voltage of the GCHT redefined and evaluated, considering the impact of carrier injection on the inversion degree of the surface in the base. Many physical effects are taken into account in this model, including channel length modulation effect, mobility degradation effect, as well as high injection effect, source/drain series resistance and body-contact resistance effect, which may result in additional gate-body bias. The model is verified by comparison between calculated results, PISCES simulated results and experimental data.     

Influence of the floating substrate potential on the characteristics of ESFI MOS transistors

A model is proposed to explain the anomalous current-voltage characteristics of ESFI MOS transistors. Due to the floating state the substrate potential of the ESFI transistor is increasing with increasing majority carrier current flowing through the substrate to source. In the region of multiplication by avalanche that effect will get quite pronounced. The change of substrate potential yields a change of the threshold voltage hereby increasing the drain current and resulting a bend in the I_D(U_D) curves. The assumptions of the model have been justified by additional experiments as with illumination of light or increased temperatures. Based on the physical model a computer program was developed to simulate the I_D(U_D) characteristics of ESFI MOS transistors of the enhancement type, resulting good agreement between measured and simulated characteristics.     

Threshold voltage controllability in double-diffused-MOS transistors

The sensitivity of double-diffused metal-oxide-semiconductor (D-MOS) transistor threshold voltage to fabrication process variations has been studied. Computed impurity profiles are used to study the process dependencies. For the double diffused process, the channel predeposition is shown to be the most critical step in threshold voltage control for long channel devices. Experimental results confirm this relationship. Process considerations appropriate for the fabrication of short channel D-MOS devices are also presented. Computed variations of threshold voltage with expected process tolerances for the channel predeposition are consistent with experimental results. Computer results show that for D-MOS deviceswith source junction depths of about 1 µm and channel lengths greater than 2 µm, threshold voltage can be controlled to ±20 percent using thermal diffusion and ±5 percent using ion implanted predeposition. Greater variation in threshold voltage is found for shorter channel lengths.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Controllable threshold voltage of a pentacene field-effect transistor based on a double-dielectric structure

The authors report controllable threshold voltage (V_th) in a pentacene field-effect transistor based on a double-dielectric structure of poly(perfluoroalkenyl vinyl ether) (CYTOP) and SiO₂. When a positive switching voltage is applied to the gate electrode of the transistor, electrons traverse through the pentacene and CYTOP layers and subsequently trapped at the CYTOP/SiO₂ interface. The trapped electrons induce accumulation of additional holes in the pentacene conducting channel, resulting in a large V_th shift from ?4.4 to +4.6 V. By applying a negative switching voltage, the trapped electrons are removed from the CYTOP/SiO₂ interface, resulting in V_th returning to an initial value. The V_th shift caused by this floating gate-like effect is reversible and very time-stable allowing the transistor to be applicable to a nonvolatile memory that has excellent retention stability of stored data.     

Continuous model for gate-induced charge in short-channel MOSFETs

The threshold voltage in a short-channel MOS transistor is a sensitive function of the effective channel length, substrate bias and the channel impurity profile. A continuous model is developed in this letter to obtain a simple analytical expression for the above described sensitivities suitable for CAD program implementation. The calculated values for the threshold voltage are compared with the measurements on MOSFETs with effective channel lengths between 9.7 ?m and 1.2 ?m.     

深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOIGCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.