80-Gb/s Low-Driving-Voltage InP DQPSK Modulator With an n-p-i-n Structure

We present a traveling-wave-electrode InP-based differential quadrature phase-shift keying modulator with a novel n-p-i-n waveguide structure. The structure features low electrical and optical propagation losses, which allow the modulator to operate at a high bit rate together with a low driving voltage and a low insertion loss. We successfully demonstrate 80-Gb/s modulation with a driving voltage of only 3 $hbox{V}_{rm pp}$ in a push–pull configuration. The chip size is just 7.5 mm$, times ,$ 1.3 mm.      

Demonstration of 20-Gb/s DQPSK With a Single Dual-Drive Mach–Zehnder Modulator

Using a single, dual-drive Mach-Zehnder modulator and high-speed electronics, differential quadrature phase-shift keying modulation and detection are demonstrated for a bit rate of 20 Gb/s. Back-to-back system performance is measured, and the receiver sensitivity is found to be -32.25 dBm.     

Rayleigh Backscattering Noise-Eliminated 115-km Long-Reach Bidirectional Centralized WDM-PON With 10-Gb/s DPSK Downstream and Remodulated 2.5-Gb/s OCS-SCM Upstream Signal

We propose a novel scheme of Rayleigh backscattering noise-eliminated, long-reach, single-fiber, full-duplex, centralized wavelength-division multiplexed passive optical network with differential quadrature phase-shift keying (DPSK) downstream and remodulated upstream using an optical carrier-suppressed subcarrier-modulation (OCS-SCM) technique and optical interleaver. The error-free transmissions of 10-Gb/s downstream and 2.5-Gb/s upstream signals are experimentally demonstrated over 115-km single-fiber bidirectional SMF-28 with less than 0.5 and 1.9 dB power penalties, respectively.      

Demonstration of Frequency-Domain Averaging Based Channel Estimation for 40-Gb/s CO-OFDM With High PMD

We experimentally demonstrate the intrasymbol frequency-domain averaging based channel estimation for a 40-Gb/s polarization-division-multiplexed coherent optical orthogonal frequency-division multiplexing signal with eight quadrature amplitude modulation under large polarization-mode dispersion, showing improved efficiency as compared to the time-domain averaging based scheme.     

Demonstration of 40-Gb/s Low-Group-Delay-Ripple Tunable Dispersion Compensator Using Angled Etalon With Multiple Reflections

We experimentally demonstrated a high-performance tunable dispersion compensator with a simple configuration using an angled etalon with multiple reflections. We developed a group-delay model of the compensator and designed to suppress the group-delay ripple (GDR). A tunable dispersion range of plusmn250ps/nm and a low <2.0-ps GDR were shown     

High-Power 25-Gb/s Electroabsorption Modulator Integrated With a Laser Diode

A high-power 1.3-mu m electroabsorption modulator integrated laser diode was developed for 100 - Gb/s Ethernet applications. The average output power exceeding 6.5 dBm and clear eye opening with dynamic extinction ratio over 7.6 dB were realized at 35 ^degC.     

Nonlinearity Limitations When Mixing 40-Gb/s Coherent PDM-QPSK Channels With Preexisting 10-Gb/s NRZ Channels

We investigate the penalties onto a 40-Gb/s polarization-division-multiplexing (PDM)-quadrature phase-shift keying caused by PDM, wavelength-division multiplexing and 10-Gb/s nonreturn-to-zero neighbor channels. Besides, we optimize the carrier phase estimation process and introduce bandgaps in the multiplex in order to contain limitations caused by cross nonlinear effects.     

A 40-Gb/s Self-Clocked Bidirectional Serial/Parallel Converter for Asynchronous Label Swapping

A novel scheme for self-clocked bidirectional serial/parallel conversion is proposed with an optically clocked transistor array (OCTA). As a result of its internal clock generation, serial-to-parallel (SP) and parallel-to-serial (PS) conversion capability, the OCTA alone realizes a single-chip low-power interface between input-output high-speed asynchronous burst optical packets and complimentary metal-oxide-semiconductor electronics, thus enabling a compact low-power solution for label swapping of optical packets. An eight-channel OCTA demonstrates self-clocked SP and PS conversion at 40 Gb/s     

10-Gb/s Inductorless CDRs With Digital Frequency Calibration

Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-$mu{hbox{m}}$ CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 ${hbox{mm}}^{2}$ and draws 36 mW from a 1.8 V supply. The measured rms jitter and peak-to-peak jitter is 8.5 ps and 42.7 ps , respectively. By using the quadrature gating technique, the second CDR circuit consumes an active area of 0.25 ${hbox{mm}}^{2}$ and its power consumption of 56 mW. The measured rms jitter and peak-to-peak jitter is 3.4 ps and 21.8 ps, respectively. The power of the second CDR circuit is higher than that of the first one but its jitter is reduced.      

Demonstration of 160- and 320-Gb/s SPECTS O-CDMA network testbeds

This letter presents a high-capacity optical code-division multiple-access (O-CDMA) network testbed based on the spectral phase-encoded time-spreading technique. Two 10-Gb/s/user O-CDMA network architectures (time-slotted and time-slotted polarization multiplexed) are investigated. The first O-CDMA network testbed architecture utilizes eight encoders and a decoder to produce 16 users equally distributed in two time slots while the second architecture evenly distributes 32 users in two time slots and two polarizations. The 16-user testbed achieved error-free performance. The 32-user testbed obtained bit-error rates below 10/sup -8/ without using forward-error-correction techniques.     

Experimental Demonstration of 1.25-Gb/s Radio-Over-Fiber Downlink Using SBS-Based Photonic Upconversion

We experimentally demonstrate a radio-over-fiber downlink system using a stimulated Brillouin scattering (SBS)-based photonic upconversion technique. The Brillouin selective amplification characteristic of SBS is incorporated to generate the 11-GHz band radio-frequency (RF) carrier. The dual-electrode Mach-Zehnder optical modulator, which is used to carry the broadband data in the optical carrier instead of the optical sideband, is adopted along with the SBS-based carrier generation setup. To vindicate the broadband capabilities of the proposed scheme, 1.25-Gb/s pseudorandom bit sequence data is carried in the optical carrier. Error-free operation of the 1.25-Gb/s downlink is achieved without critical power penalties after the 13-km fiber transmission.     

Investigation of 43-Gb/s Transmission With a Wavelength Preserving SOA-Based Optical Regenerator

Transmission with cascaded optical regeneration based on synchronous modulation combined with optical reshaping by cross-gain compression in a semiconductor optical amplifier is investigated at 43 Gb/s over transoceanic distances (10 000 km). The proposed optical regenerator configuration performs signal reshaping and retiming while preserving the input signal wavelength. The regenerator cascadability properties are investigated using a reconfigurable loop to assess the impact of different inter-regeneration spacing on the transmission signal properties.      

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- $mu$m complementary metal–oxide–semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80–1.52 pJ/b. This work demonstrates a 15.0%–67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.      

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

2R-Regeneration of an 80-Gb/s RZ-DQPSK Signal by a Nonlinear Amplifying Loop Mirror

The performance of a nonlinear amplifying loop mirror as a 2R-regenerator for an 80-Gb/s return-to-zero differential-quadrature-phase-shift-keyed signal has been investigated experimentally. A significant eye-opening improvement and a negative power penalty of up to 2.6 dB were obtained.     

42.8-Gb/s RZ-DQPSK Transmission With FBG-Based In-Line Dispersion Compensation

Phase ripple impairments induced through cascaded fiber Bragg gratings (FBGs) are discussed for 42.8-Gb/s transmission. We show the feasibility of transmission over 1140 km (12 times 95 km) using return-to-zero differential quadrature phase-shift keying modulation and FBG-only dispersion compensation. We further compare FBGs with dispersion-compensating fiber for dispersion compensation and analyze the influence of wavelength detuning.     

Stable 100-Gb/s POLMUX-DQPSK Transmission With Automatic Polarization Stabilization

The reliability of 100-Gb/s polarization-multiplexed return-to-zero differential quadrature phase-shift keying transmission is demonstrated exploiting direct detection and automatic polarization stabilization. We experimentally verified a 2-dB chromatic dispersion tolerance of 100 ps/nm. Long-term stability has also been assessed by sampling the bit-error rate every 3 min over a continuous period of 8 h. Measurements are performed both in back-to-back and after 8.8-km uncompensated standard single-mode fiber, in the presence of a polarization scrambler.      

40-Gb/s All-Optical Packet Switching With a Distributed-Feedback Laser as All-Optical Flip-Flop

All-optical flip-flops (AOFFs) have recently received increased attention as elements for all-optical packet-switched networks. In this letter, we use a single off-the-shelf distributed- feedback laser as AOFF to switch 40-Gb/s packets with a guard time as low as 150 ps.      

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mWbit-interleaved 8:1 multiplexers with a 0.15-μm CMOS technology

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-μm CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers     

132.2-Gb/s PDM-8QAM-OFDM Transmission at 4-b/s/Hz Spectral Efficiency

In this letter, we investigate 132.2-Gb/s polarization- division-multiplexed orthogonal frequency-division-multiplexing (PDM-OFDM) transmission at 25-GHz channel spacing. We show that the nonlinear tolerance is dependent on the OFDM symbol length. By using 14.4-ns-long OFDM symbols, 7 $, times ,$132.2-Gb/s transmission of PDM-OFDM at 4-b/s/Hz spectral efficiency is reported over 1300-km standard single-mode fiber.