低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

基于暂态电流的高压输电线的故障检测

针对高压输电线故障存在检修困难、故障点定位误差较大和易受外部因素影响等问题,本文根据行波传输理论以故障电流行波为测量对象,提出一种基于暂态电流的高压输电线路单端故障测距算法。现以某区电网高压输电线路故障为例,利用MATLAB构建仿真模型进行仿真。由仿真结果可以看出：所采用的故障测距算法不仅计算简单,而且测距精度较高。     

A fault simulation method: Parallel pattern critical path tracing

We present a fast fault simulation algorithm for combinational circuits which combines parallel pattern evaluation and critical path tracing. When the number of faults is large, our algorithm exploits the full advantages of critical path tracing. As fault dropping progresses, the overhead for critical path tracing surpasses its advantages. On the other hand, the efficiency of Parallel Pattern Single Fault Propagation (PPSFP) increases rapidly since relatively few undetected faults remain, and they tend to be inactive. To avoid the overhead of critical path tracing and achieve the advantages of PPSFP, dynamic update of node classes is used to produce a smooth transition from critical path tracing to PPSFP. By using this approach, we get high performance for both small and large numbers of test patterns. Also, preprocessing related to structure analysis is avoided while achieving almost all of its advantages.This work was supported in part by National Science Foundation grant MIP-9003292.     

A New Approach to Software-Implemented Fault Tolerance

A new approach for providing fault detection and correction capabilities by using software techniques only is described. The approach is suitable for developing safety-critical applications exploiting unhardened commercial-off-the-shelf processor-based architectures. Data and code duplications are exploited to detect and correct transient faults affecting the processor data segment, while control flow instruction duplication is used for detecting and correcting faults affecting the code segment. Results coming from extensive fault injection campaigns showed the effectiveness and the limitations of the method.     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

Fault diagnosis in wireless sensor network using clonal selection principle and probabilistic neural network approach

The fault diagnosis in wireless sensor networks is one of the most important topics in the recent years of research work. The problem of fault diagnosis in wireless sensor network can be resembled with artificial immune system in many different ways. In this paper, a detection algorithm has been proposed to identify faulty sensor nodes using clonal selection principle of artificial immune system, and then the faults are classified into permanent, intermittent, and transient fault using the probabilistic neural network approach. After the actual fault status is detected, the faulty nodes are isolated in the isolation phase. The performance metrics such as detection accuracy, false alarm rate, false‐positive rate, fault classification accuracy, false classification rate, diagnosis latency, and energy consumption are used to evaluate the performance of the proposed algorithm. The simulation results show that the proposed algorithm gives superior results as compared with existing algorithms in terms of the performance metrics. The fault classification performance is measured by fault classification accuracy and false classification rate. It has also seen that the proposed algorithm provides less diagnosis latency and consumes less energy than that of the existing algorithms proposed by Mohapatra et al, Panda et al, and Elhadef et al for wireless sensor network.     

一种基于存储器故障原语的March测试算法研究

研究高效率的系统故障测试算法,建立有效的嵌入式存储器测试方法,对提高芯片良品率、降低芯片生产成本,具有十分重要的意义.从存储器基本故障原语测试出发,在研究MarchLR算法的基础上,提出March LSC新算法.该算法可测试现实的连接性故障,对目前存储器的单一单元故障及耦合故障覆盖率提升到100%.采用March LSC算法,实现了内建自测试电路(MBIST).仿真实验表明,March LSC算法能很好地测试出嵌入式存储器故障,满足技术要求.研究结果具有重要的应用参考价值.     

Extended selection of switching target faults in CONT algorithm for test generation

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.     

模拟电路模块级软故障特征的提取与故障诊断

介绍了一种模拟电路故障诊断中功能模块级的单模块软故障模型的建立理论和特征提取的方法,运用该方法提取的单模块故障特征不仅可以有效区分单模块电路中的各类故障,而且单模块电路的故障特征还可以在多模块电路的单故障和多故障的情况下应用。仿真结果表明,通过采样电路输出并进行相应的信号处理来提取故障模型,可以准确地定位多模块故障电路的故障部位。     

Multifault diagnosis in WSN using a hybrid metaheuristic trained neural network

Wireless sensor networks are susceptible to failures of nodes and links due to various physical or computational reasons. Some physical reasons include a very high temperature, a heavy load over a node, and heavy rain. Computational reasons could be a third-party intrusive attack, communication conflicts, or congestion. Automated fault diagnosis has been a well-studied problem in the research community. In this paper, we present an automated fault diagnosis model that can diagnose multiple types of faults in the category of hard faults and soft faults. Our proposed model implements a feed-forward neural network trained with a hybrid metaheuristic algorithm that combines the principles of exploration and exploitation of the search space. The proposed methodology consists of different phases, such as a clustering phase, a fault detection and classification phase, and a decision and diagnosis phase. The implemented methodology can diagnose composite faults, such as hard permanent, soft permanent, intermittent, and transient faults for sensor nodes as well as for links. The proposed implementation can also classify different types of faulty behavior for both sensor nodes and links in the network. We present the obtained theoretical results and computational complexity of the implemented model for this particular study on automated fault diagnosis. The performance of the model is evaluated using simulations and experiments conducted using indoor and outdoor testbeds.     

一种动态电流测试产生方法的SPICE模拟验证

数字电路状态发生改变时,数字电路中的逻辑跳变直接影响电路中的动态电流.基于布尔过程的波形模拟器能够快速准确地对电路进行模拟,其结果既能反映电路的逻辑特性又能反映电路的定时特性.利用波形模拟器可以准确的了解电路中跳变的情况.本文利用波形模拟器改进并实现了一种基于逻辑跳变计数的动态电流测试方法.对于S208电路中的部分开路故障和延时故障,本文用该方法产生了一组测试结果,并利用SPICE软件对这些测试结果进行了模拟实验.模拟结果表明,对于某些故障,测试向量对能够使故障电路的动态电流和无故障电路的动态电流产生较大的差别.通过比较两者平均动态电流的大小,我们能够区分出故障电路和无故障电路.实验结果验证了本文中的动态电流测试产生方法的有效性和可行性.     

分级ad hoc网络中的一种应用层故障诊断算法

针对应用层故障提出了一种故障诊断算法——“基于簇的比较诊断算法”，该算法在分级ad hoc网络中利用簇首对簇内节点的集中控制功能优化了诊断过程，实现了诊断期问网络拓扑变化时对移动节点的诊断。证明了算法的正确性，并分析了算法的性能。仿真结果表明，该算法突破了“基于比较的故障诊断”在诊断过程中网络拓扑不能发生变化的限制，大大减小了“基于比较的故障诊断算法”由于诊断消息的洪泛导致的大量的系统开销。     

多源导航系统软、硬故障检测新方法研究

故障检测和隔离对提高无人机的导航精度和可靠性有重要意义.针对残差卡方算法对小值软故障灵敏度差,改进序贯概率比(SPRT)算法无法判断故障结束时间的缺陷,提出了一种联合故障检测算法.该算法依靠残差卡方算法判断故障结束时间,从而及时对改进SPRT算法检测值进行修正,使改进SPRT算法能继续检测非第一次故障.改进SPRT算法对故障的灵敏度高,且残差卡方算法能准确判别故障结束时间.仿真结果表明,该综合算法对小值软故障、大值阶跃故障都有很好的检测效果,有效提高了系统的故障检测能力及灵敏度,增强了组合导航系统的可靠性.     

基于特征结构配置的飞控系统故障检测与诊断

针对具有未知扰动输入的飞行控制系统,运用特征值配置设计了一种用于故障检测和诊断的观测器,他通过对观测器进行左特征向量的配置使得残差与干扰分布方向正交,故障检验残差r与未知输入干扰d之间的传递函数阵为零,从而使残差与干扰直接解耦.通过这种方法,残差信号得以对干扰具有鲁棒性,使FDI算法不受系统不确定性干扰的影响,提高系统故障诊断的可靠性和精度.同时通过残差信号估计故障,能在线辨识故障的形态,仿真结果验证了该方法的有效性.     

Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system

In this work different VHDL-based fault injection techniques (simulator commands, saboteurs and mutants) have been compared and applied in the validation of a fault-tolerant system. Some extensions and implementation designs of these techniques have been introduced. As a complement of these injection techniques, a wide set of fault models (including several non-usual models) have been implemented. We have injected both transient and permanent faults on the system model, using two different workloads, with the help of a fault injection tool that we have developed. We have studied the pathology of the propagated errors, measured their latencies, and calculated both detection and recovery coverages. Results show that coverages for transient faults can be obtained quite accurately with any of the three techniques. This enables the use of different abstraction level models for the same system. We have also verified significant differences in implementation and simulation cost between the studied injection techniques.     

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.     

基于故障注入的基准电路故障响应分析

为了提高集成电路的成品率,试图采用更简便有效的方法测试芯片,并获得反映电路特性的故障响应率,在进行电路功能仿真(前仿真)或电路时序仿真(后仿真)的过程中,对电路注入单故障或多故障,然后在电路存在故障的情况下,模拟电路的行为,获得电路的故障响应率.实现了一个通用的数字电路"故障响应分析"程序,他模拟电路注入故障,收集模拟结果,通过分析获取电路的故障响应率.     

小波变换在电网故障诊断中的应用

故障特征作为故障诊断的重要信息,其提取方法研究备受关注。为提取电网短路故障的特征信息,在Matlab的Simpowersystem电力系统建模的基础上,运用小波变换的方法,对短路故障工况的暂态过程进行了分析和特征提取,其所提取的均方根值与不同的短路故障之间存在映射关系。证明了运用小波变换进行特征信息的提取,在电网短路故障诊断中具有一定的应用价值。