The effects of parasitic capacitance on the noise figure of MESFETs

The parasitic capacitance due to the gate pad and the gate feed area of a MESFET plays an important role in the low-noise performance of the device. Its effects on the noise figure have been measured and analyzed for π-FET device geometries. It is shown that there is an optimum unit gate width for the minimum noise figure. This optimum unit gate width depends on the device structure and the processing parameters. When the effects of parasitic capacitances are included, H. Fukui's (1979) equation predicts noise figures that are in good agreement with the experimental data     

AlGaN/GaN HEMT器件工艺的研究进展

首先论述了Al GaN/GaN高电子迁移率晶体管(HEMT)在微波大功率领域的应用优势和潜力;其次,介绍并分析了影响Al GaN/GaN HEMT性能的主要参数,分析表明要提高Al-GaN/GaN HEMT的频率和功率性能,需改善寄生电阻、电容、栅长和击穿电压等参数。然后,着重从材料结构和器件工艺的角度阐述了近年来Al GaN/GaN HEMT的研究进展,详细归纳了目前主要的材料生长和器件制作工艺,可以看出基本的工艺思路是尽量提高材料二维电子气的浓度和材料对二维电子气的限制能力的同时减小器件的寄生电容和电阻,增强栅极对沟道的控制能力。另外,根据具体情况调节栅长及沟道电场。最后,简要探讨了Al GaN/GaN HEMT还存在的问题以及面临的挑战。     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.     

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance $C_{rm of}$ dominates around 25% of the intrinsic gate capacitance $(C_{rm gint})$ in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor $C_{rm of}/C_{rm gint}$ above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.      

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

Application of the Shubnikov-de Haas oscillations in the characterization of Si MOSFET's and GaAs MODFET's

The Shubnikov-de Haas magnetoconductance oscillations were used to measure directly the gate-to-channel capacitance of Si MOSFET's and GaAs MODFET's, to detect the onset of parallel conduction in GaAs MODFET's, and to provide an approximate measure of channel length in sub-100-nm channel of Si MOSFET's. The measurements do not require knowledge of any device parameters, are immune to any gate parasitic capacitance, and are independent of source and drain series resistances. One needs to know only the magnetic field, the oscillation period (for gate-to-channel capacitance measurement), the gate voltage (for detection of the onset of parallel conduction), and the number of oscillation peaks (for the channel length characterization). Experimental results have shown that the characterization methods are accurate, and can be applied to FET's with sub-100-nm channel length.     

An analytical approach to the capacitance-voltage characteristicsof double-heterojunction HEMTs

The two-dimensional electron gas concentration and capacitance in AlGaAs/GaAs/AlGaAs double-heterojunction high-electron-mobility transistors (DH-HEMTs) are calculated as a function of gate voltage using simple iterative solutions of analytical equations. The results show very good agreement with experimental data, as well as with characteristics predicted by complex numerical methods. The calculations are extended to predict the capacitance-voltage characteristics in the presence of parasitic conduction when the gate does not fully control the two-dimensional gas. The developed charge control and capacitance models are easy and inexpensive to run. They are therefore very useful for microwave circuit designs. Furthermore, they can be used for performance prediction and design optimization of DH-HEMTs. The influence of technological parameters, such as layer thickness and aluminum composition, on device performance are presented     

GaAs ultra-high-frequency dividers with advanced SAINT FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.     

dV/dt对IPM中IGBT栅极电路的影响分析

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled.     

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Microwave-Rectification RFI Response in Field-Effect Transistors

This paper discusses the rectification of microwave energy in low-medium frequency feld-effect transistors (FET's) and develops a small-signal model for RHI noise analysis in low-frequency linear circuitry. The modeling procedure centers on a Taylor series expansion of the gate voltage-drain current characteristic which shows a small increase in drain current due to a nicrowave voltage at the gate. The increase in drain current is proportional to the variation in transconductance with gate voltage, and the square of the microwave voltage. Analysis of the microwave power in the transistor shows that critical parameters in determnination of the sensitivity are the gate capacitance and the real part ofthe device input impedance, which ultimately is limited by the parasitic resistance between the active channel and contacts.     

具有高掺杂表面层和阶梯栅结构SiC MESFETs双沟道器件研究

An improved dual-channel 4H-SiC MESFET with high doped n-type surface layer and step-gate structure is proposed, and the static and dynamic electrical performances are analyzed.A high doped n-type surface layer is applied to obtain a low source parasitic series resistance, while the step-gate structure is utilized to reduce the gate capacitance by the elimination of the depletion layer extension near the gate edge, thereby improving the RF characteristics and still maintaining a high breakdown voltage and a large drain current in comparison with the published SiC MESFETs with a dual-channel layer.Detailed numerical simulations demonstrate that the gate-to-drain capacitance, the gate-to-source capacitance, and the source parasitic series resistance of the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.     

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.     

一种CMOS工艺离子敏场效应型晶体管的模型

采用CMOS工艺可以实现离子敏场效应型晶体管(ISFET),若在栅极氧化层之上保留多晶硅层,并通过引线使其与 外界的金属层相连作为悬浮的栅极,可实现悬浮栅结构ISFET.从ISFET的传感机理出发,根据表面基模型,利用HSPICE建 立了悬浮栅结构ISFET的物理模型.以该模型为研究对象,探讨了薄膜等效电阻、薄膜等效电...