一种0.35 μm CMOS高精度Σ-Δ A/D转换器

提出了一种应用于MEMS压力传感器的高精度Σ-Δ A/D转换器。该电路由Σ-Δ调制器和数字抽取滤波器组成。其中,Σ-Δ调制器采用3阶前馈、单环、单比特量化结构。数字抽取滤波器由级联积分梳状(CIC)滤波器、补偿滤波器和半带滤波器(HBF)组成。采用TSMC 0.35 μm CMOS工艺和Matlab模型对电路进行设计与后仿验证。结果表明,该Σ-Δ A/D转换器的过采样比为2 048,信噪比为112.3 dB,精度为18.36 位,带宽为200 Hz,输入采样频率为819.2 kHz,通带波纹系数为±0.01 dB,阻带增益衰减为120 dB,输出动态范围为110.6 dB。     

低电压Σ-Δ调制器关键技术及设计实例

介绍了低电压开关电容Σ-Δ调制器的实现难点及解决方案,并设计了一种1 V工作电压的Σ-Δ调制器.在0.18 μm CMOS工艺下,该Σ-Δ调制器采样频率为6.25 MHz,过采样比为156,信号带宽为20 kHz;在输入信号为5.149 kHz时,仿真得到Σ-Δ调制器的峰值信号噪声失真比达到102 dB,功耗约为5 mW.     

一种高精度音频Σ-Δ调制器的研究北大核心

介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器。该电路采用Chartered 0.5μm标准CMOS工艺实现,工作电源电压为5V,在工作频率为6.144MHz、过采样率为128时,输入带内信噪比可达107dB。     

一种高精度音频Σ-Δ调制器的研究

简要介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器.该电路采用Chartered 0.5 μm标准CMOS工艺实现,工作电源电压为5 V,在工作频率为6.144 MHz、过采样率为128时,输入带内信噪比可达107 dB.     

一种低电压3阶4位前馈Σ-Δ调制器

介绍了一种应用于无线通信领域的低电压、带有前馈结构的3阶4位单环Σ-Δ调制器。为了降低Σ-Δ调制器的功耗,跨导放大器采用了带宽展宽技术。采用TSMC 0.13 μm CMOS工艺对电路进行仿真,仿真结果显示,当工作电压为1.2 V、采样频率为64 MHz、过采样比为16、信号带宽为2 MHz时,电路的SNDR达81 dB,功耗仅为7.78 mW。     

三阶1-1-1级联Σ-Δ调制器的设计及仿真

采用MASH结构,设计了一款三阶(1-1-1)级联Σ-Δ调制器;讨论了各个模块的增益系数,设计了数字校正电路,并运用Matlab/Simulink对调制器进行了行为级仿真.当输入信号带宽为20 kHz,过采样比为64时,仿真模型得到87.7 dB的信噪比,精度为14.28位.与其他结构的调制器相比,该调制器更加稳定,动态范围更大,可应用于处理音频信号的A/D转换器.     

窄带射频接收系统中带通Σ-Δ调制器的设计

设计了一种适用于无线窄带射频接收系统的带通Σ-Δ调制器,并将其成功集成于一个无线射频收发芯片之中.该调制器采用0.35 μm CMOS工艺实现,采用斩波-稳零,动态元件匹配,以及正交采样等技术,提高系统的信噪比,并解决通道间失配的问题.模拟结果表明,该电路在30 kHz带宽内,信噪比为83.4 dB,而两个通道消耗的总电流仅为1 mA.     

一种0.18m单层多晶硅CMOS音频-调制器

设计了一种应用于18位高精度音频模数转换器(ADC)的三阶Σ-Δ调制器。调制器采用2-1级联结构,优化积分器的增益来提高调制器的动态范围。采用栅源自举技术设计输入信号采样开关,有效提高了采样电路的线性度。芯片采用中芯国际0.18μm混合信号CMOS工艺,在单层多晶硅条件的限制下,采用MIM电容,实现了高精度的Σ-Δ调制器电路。测试结果表明,在22.05kHz带宽内,信噪失真比(SNDR)和动态范围(DR)分别达到90dB和94dB。     

14-b400-ksps 2.5-mW连续时间Σ-Δ调制器

连续时间Σ-Δ调制器较之传统的开关电容Σ-Δ调制器具有更低的功耗、更小的面积,以及集成抗混叠滤波器等诸多优势。设计了一种应用于低中频GSM接收机的4阶单环单比特结构的连续时间Σ-Δ调制器。在调制器中,采用了开关电容D/A转换器,以降低时钟抖动对性能的影响。仿真结果显示,在1.8 V工作电压2、00 kHz信号带宽、0.18μm CMOS工艺条件下,采样频率21 MHz,动态范围(DR)超过90 dB,功耗不超过2.5 mW。     

一种用于过采样Σ-Δ A/D转换器的抽取滤波器

采用0.8 μm CMOS工艺,实现了一种用于过采样Σ-Δ A/D转换器的数字抽取滤波器.该滤波器采用多级结构,梳状滤波器作为首级,用最佳一致逼近算法设计的FIR滤波器作为末级,并通过位串行算法硬件实现.芯片测试表明,该滤波器对128倍过采样率、2阶Σ-Δ调制器的输出码流进行处理得到的信噪比为75 dB.     

Sigma-Delta调制及其在低噪声DC-DC变换器的应用

分析了传统PWM调制和Sigma-Delta调制在噪声性能方面的差异,以及它们对DC-DC变换器输出噪声的影响。在Chartered 0.35μm CMOS工艺条件下实现了一个基于二阶Sigma-Delta调制的低噪声DC-DC变换器,并对其中Sigma-Delta调制模块进行了流片验证。测试结果表明,Sigma-Delta调制模块能够将环路带宽内噪声抑制到-50 dB左右,并且未引入与开关频率有关的谐波成分。仿真结果表明,DC-DC变换器输出电压噪底能够达到-60 dB以下。     

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator.A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator.The proposed modulator uses sampling capacitor sharing switched capacitor integrator,and achieves a very small feedback coefficient by a series capacitor network,and those two techniques can dramatically reduce capacitor area.Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation.This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and-1 MHz IF with 48 MHz clock.The chip is fabricated with SMIC 0.18 μm CMOS technology,it achieves a total power current of 2.1 mA,and the chip area is 0.48 mm2.     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

一种10 MHz带宽70 dB动态范围连续时间Sigma-Delta调制器

介绍了4阶反馈型连续时间Sigma-Delta调制器从顶层到底层的详细设计过程。采用数字置乱技术,降低失配对输出杂散的影响,使失配产生的谐波被转换为噪声,并被移出通带外。将谐振腔内嵌于调制器环路中,以改善带内信噪比。采用三级前馈型放大器,调制器具备更高的能效。该调制器基于65 nm CMOS工艺设计并流片。测试结果表明,在时钟频率为614.4 MHz、信号带宽为10 MHz时,调制器的SNDR为70.1 dB,动态范围达70 dB。功耗为77 mW。该调制器芯片的内核面积为4.50 mm²。     

Noise analysis and characterization of a sigma-delta capacitive microaccelerometer

This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop.     

Low Distortion and Swing Suppression Sigma-Delta Modulator with Extended Dynamic Range Scheme

This work presents a new low distortion and swing suppression second order sigma-delta modulator with extended dynamic range scheme. The proposed modulator is based on the dual-quantizer architecture and can effectively extend the dynamic range by only adding two simple digital filters in the digital circuit. The techniques of low distortion and swing suppression integrator designs are also employed in the new architecture. Accordingly, this new architecture can improve the circuitry nonlinearity, and the in-band noise can be significantly suppressed to achieve a high resolution in mid or wide bandwidth applications. A second order SDM for Bluetooth application with bandwidth of 500 KHz and sampling frequency of 40 MHz was designed and implemented. The peak SNDR of the experimental SDM is 78 dB.     

双采样技术在三阶sigma-delta调制器中的应用

近年发展的双采样技术（ｄｏｕｂｌｅ ｓａｍｐｌｉｎｇ）是提高ｓｉｇｍａ－ｄｅｌｔａ调制器信噪比的一种有效的方法,而电容的失配是影响其信噪比的重要因素。分析表明,双采样技术在三阶系统中的应用,电容失配引起前馈信号混叠,由此产生的噪声对系统信噪比的影响不可忽略。本文提出了一种结合ＩＬＡ ＤＡＣ「２」和前端完全浮动电容结构的电路形式,将这种结构应用在第二级调制器的积分器上,使双采样电容失配产生的噪声远小     

The Structure of Quantization Noise from Sigma-Delta Modulation

When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.