一种简单的S参数去嵌入技术

介绍了在低成本夹具上，任意微带结构二端口网络S参数去嵌入的方法；该方法用于获取放大器模块的S参数，根据这些参数设计的C波段的放大器实测结果与仿真一致。     

一种去嵌入射频测量技术

去嵌入是一种射频微波精确测量技术。本文介绍了一种新型的去嵌入测量技术。该方法只需要一个对称的直通微带结构就能完成去嵌入。最后利用该方法对0603封装的电感进行了测量,并提取了精确测量后的电感模型。结果表明本去嵌入方法可以应用于射频PCB上器件模型的精确测量和模型提取。     

在低成本测试夹具上实现对表面贴装射频元器件的精确去嵌入

简介 射频工程师通常使用矢量网络分析仪(VNA)测量射频元器件的S参数,以便对其特性进行表征并进行后续设计.他们在测量过程中遇到的一个问题是,这些元器件往往是表贴封装的,不能直接与VNA连接.     

Infiniband电缆组件测量夹具S参数的一致性测试

S参数测量,如插入损耗、回波损耗和频域串扰正日益成为高速数字标准电缆组件一致性测试程序的一部分。例如,当前Infiniband规范要求,电缆差分插入损耗在1.25Ghz时,小于10dB。PCIExpress和串行ATAII及X A U I等其它标准也都有类似的测量要求。传统S参数测量一直使用频域矢量网络     

2009IEEEEMC学术研讨会——获奖文章（一）

针对单端传输线的去嵌入已经被广泛应用,但还没有针对被耦合传输线的去嵌入技术,文章提出了针对被耦合传输线的去嵌入技术,这种去嵌入技术采用单端TRL校准图,而其结果可以通过矢量网络分析仪（VNA）的误差校正数据直接得到。     

一种“L-2L”传输线去嵌入方法的优化分析

介绍了一种基于硅基微波共面波导传输线的"L-2L"去嵌入技术的改进方法。该方法可更加精确地剥离在片器件S参数中探针焊盘寄生效应的影响。利用ADS软件对无焊盘的理想传输线结构进行了电磁仿真,确立了去嵌入结果精确度的判定标准。使用GSG微波探针提取了测试样品的S参数,推导了π型寄生参量等效电路模型中并联导纳Y不同位置(m=0,0.5,1)下左、右探针焊盘的ABCD矩阵,得到了去嵌入后在片器件的本征传输特性S参数,并结合电磁仿真对比。结果表明:m=1时,其S参数曲线与仿真结果最为接近(平均偏差量ΔS_(11)=18.431,ΔS_(21)=4.405,ΔS=11.418)。对于不同在片测试器件需要着重考虑m的取值。     

Using a Single-ended TRL Calibration Pat-tern to De-embed Coupled Transmission Lines

针对单端传输线的去嵌入已经被广泛应用但还没有针对被耦合传输线的去嵌入技术。文章提出了针对被耦合传输线的去嵌入技术,这种去嵌入技术采用单端TRL校准图,而其结果可以通过矢量网络分析仪(VNA)的误差校正数据直接得到。     

SOLT校准方法及其在射频测量中的应用

分析了矢量网络分析仪测试系统的误差来源,给出二端口SOLT校准的12项误差模型,由此推导了待测元件的真实S参数,并且详细讲述了SOLT校准件的制作方法,确定出开路件的边缘电容。最后,使用自制的PCB夹具测量了0603封装的电感和电容．对校准前后的测量数据进行了对比、分析,并成功地提取了封装后的模型参数,结果证明该方法可以用于射频夹具测量的校准。     

非同轴微波器件测试夹具的设计与应用

由于非同轴微波器件接口的特殊性,无法直接与同轴接口的矢量网络分析仪相连进行测试,非同轴器件的微波性能测试面临较大的困难,目前,国内非同轴器件的测试技术已严重滞后其设计开发工作。对非同轴微波器件接口进行了深入研究,设计了针对非同轴微波器件测试的分体式夹具,解决了去嵌入技术问题,并以实例验证了该测试装置的正确性。大量测试表...     

单端口声表面波谐振器在片去嵌方法分析

为了准确地设计声表滤波器,需要从参考声表面波(SAW)谐振器的测量值中提取精确的材料参数。测量SAW谐振器时,单个谐振器无法直接进行测试,需要引出传输线并使用GSG或GS探针进行测量,消除传输线影响的去嵌入过程对于SAW谐振器材料参数的准确提取非常重要。该文介绍了几种声表面波谐振器的去嵌入技术,包括Open-Short算法、电磁仿真方法、分段等效电路模型方法、集总参数等效电路法。通过实例验证了几种常用的去嵌方法并对其进行了分析。     

General Design for Test Guidelines for RF IC

While the cost of silicon drops over years, the IC test cost basically stays flat. Hence, the percentage of the test cost in the overall chip cost increases significantly. For the total test cost, the RF test cost is a major contributor due to its tester requirement as well as the complexity of the RF parametric and functional tests. Design for Test (DFT) is a natural step to take to reduce the overall testing cost when the cost of the silicon to implement many Built-In Self Test (BIST) is virtually negligible. This article presents general guidelines for the RF IC, especially for the System on Chip (SoC) and System in Package (SiP) parts. It discusses the specific guidelines for DFT in order to reduce the RF test cost while still keeping acceptable test quality for both RF parameters and functionalities.     

基于Ultra-FLEX测试系统的集成电路测试开发

在半导体技术高速发展的今天,对集成电路的测试要求越来越高,测试开发的难度、复杂度都在增加,如何应对当前集成电路的测试需求,成为测试开发者需要考虑的问题。Ultra-FLEX测试系统是新一代的测试系统,用以应对当今的测试需求。文章介绍了Ultra-FLEX测试系统的硬件资源,列举了部分模块及其功能和参数;描述了一般集成电路测试开发的流程,并以数字集成电路为例介绍了相关测试内容;介绍了Ultra-FLEX测试系统的软件环境,列举了测试程序构成要素以及各自功能;介绍了Ultra-FLEX测试系统的程序调试环境,测试系统提供的调试工具以及调试方法。     

BSIM射频模型综述

CMOS集成电路技术的进一步发展和不断出现的新技术要求模型研究人员持续改进和增强VLSI电路设计和模拟的集约模型。美国Berkeley加州大学的BSIM团队对业界标准芯片仿真物理模型BSIM进行了不断的改进与开发。主要介绍BSIM系列模型在RF应用方面的改进。相对于BSIM3v3,BSIM4添加了更多真实器件效应,BSIM5和BSIM6是为了满足射频(RF)和高速CMOS电路模拟要求而发展的新一代物理基础的BSIM模型,具有对称、连续和参数少的特点。BSIM6可用于低压低功耗的RF和模拟设计。     

Test Fixtures for RF Susceptibility Testing

The most likely standard test fixture for RF susceptibility testing is the twin-strip transmission line, or its half-space counterpart. Its capacitance per meter (length) is 2? or 4?; characteristic impedance Zc= Z0/2 or Z0/4; voltage gradient Ez = V/w or 2 V/w; magnetic field Hy = V/w Z0 or 2 V/w Z0, respectively.     

数字IC的射频电磁发射模型建模方法

针对传统方法无法直接得到芯片内核到外部引脚传输路径特性的问题,提出了一种简单有效的数字IC的电磁发射建模方法。该模型由内部活动模型和传输路径模型组成。利用嵌入式环形振荡器的直流响应和外源射频干扰效应,直接测量出芯片内核到外部引脚路径的电压传输率,有效抽取出传输模型结构。利用晶体管级Hspice仿真得到内部活动模型,获得了完整的电磁发射模型。在SMIC 130 nm 工艺的测试芯片上应用该模型,对比模型仿真结果与实物测量结果,验证了该模型建模方法的正确性。该方法可用于系统设计阶段,对数字IC的电磁发射进行预测,使系统能满足电磁发射的要求。     

基于ATE的卫星导航射频芯片测试技术

卫星导航射频芯片是导航系统中的关键部分,其指标的优劣决定着导航系统的导航精度。通过分析卫星导航射频芯片的结构特点,针对主要参数进行了测试分析。在基于集成电路自动测试系统(ATE)的基础上,结合射频测试设备实现卫星导航射频芯片的性能测试。该技术对基于ATE的射频芯片测试均具有借鉴意义。     

Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications

In the recent past, with the emergence of System-on-Chip (SoC), focus has shifted towards testing system specifications rather than device or module specifications. While the problem of test accessibility for test stimulus application and response capture for such high-speed systems remains a challenge to the test engineers, new test strategies are needed which can address the problem in a practical manner. In this paper, the problem of testing the transmitter and the receiver subsystems of a RF transceiver for system level specification is addressed. Instead of using different conventional test stimuli for testing each of the system level specifications of RF subsystems, a specially crafted test stimulus is used for testing all the specifications from the response of the subsystem-under-test. A new simulation approach has also been developed to perform fast behavioral simulations in frequency domain for the system-under-test. In the test method, frequency domain test response spectra are captured and non-linear regression models are constructed to map the spectral measurements onto the specifications of interest. In the presented simulation results, the test stimuli have been validated using netlist level simulation of the subsystem-under-test and specifications have been predicted within an error of ±3% of the actual value.Soumendu Bhattacharya was born in Calcutta, India, in 1978. He received his Bachelors degree from Indian Institute of Technology, Kharagpur, India, in 2000. In 2002, he received the M.S.E.E. degree in electrical engineering from Georgia Institute of Technology, Atlanta, USA. He is currently working toward his Ph.D. degree. In the summer of 2001, he worked as a summer intern in National Semiconductor, Santa Clara, CA, USA. His research interests are in the area of test generation for mixed-signal and RF circuits and systems and design-for-test.Achintya Halder received the B.S. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, in 1998. He worked as an IC design engineer with Texas Instruments until 2000. Currently, he is a Ph.D. student and a research assistant with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta. His research area is analog/RF and mixed signal testing.Ganesh P. Srinivasan received the B.E. degree in Electronics and Communication Engineering from the National Institute of Technology and Science, University of Madras, Chennai (Madras), India, in 2002. He received the M.S. degree in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, GA, in 2004 and is currently pursuing his Ph.D. degree in Electrical and Computer Engineering at the Georgia Institute of Technology, Atlanta, GA. His research interests include low cost testing approaches for analog/RF and mixed-signal circuits, and improving performance of low cost testers for enabling high quality tests.Abhijit Chatterjee received the Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1981, the M.S. degree in electrical engineering and computer science from University of Illinois at Chicago in 1983 and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Until December 1992, he was a Research Staff Member at the General Electric Research and Development Center in Schenectady, NY. His work has been cited by the Wall Street Journal and presented on a Japanese network TV program called High Tech Shower International. He is a collaborating partner in NASAs New Millennium Project. Dr. Abhijit Chatterjee is also the author of one U.S. patent and has over one hundred publications in referenced journals and conferences.     

测试系统中射频网络自动切换的研究

对测试系统中射频网络自动切换的各种设计方案进行了全面分析比较,并提出了一种高适配能力的设计方案,基于此方案设计的混合式智能型开关矩阵,解决了自动测试设备与各种被测单元适配难的问题.用一套测试装置完成多种测试,而不需要频繁地断开和连接.实现测试过程的自动化,提高测试效率并且降低成本.     

吉时利用于高速产品测试的RF测试方案

吉时利仪器公司近期发布的2800RF功率分析仪，主要用于无线电话、RFIC功率放大器和相关RF器件的高速测试。2800采用独特的设计结构，首次提供了可满足更高速产品测量需求的RF功率测试，并具有优秀的测试质量和比传统的产品更低廉的成本。高速的测试可以从根本上缩短测试时间，有效地降低测试成本。     

基于USB接口的射频IC卡系统

介绍了一种带有USB接口的射频IC卡系统,阐述了该系统的工作原理.经过方案对比,选用USBN9603作为USB接口控制芯片,构成USB接口电路,可以使设计简单,尤其适合于产品的改型设计.给出了USB设备的软件设计方法,并给出了单片机与上位管理机通信的程序流程.由于采用USB接口,可以克服以往IC卡系统不支持热插拔和不能灵活与外设连接的缺点.