Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA

A new technique for improving the transconductance and low frequency output impedance of recycling folded cascode (RFC) amplifiers is presented. This enhancement was achieved by using a positive feedback and upgrading the recycling structure. The new structure profits from better transconductance, slew rate, and DC gain in comparison with conventional folded cascode (FC) amplifier. Moreover, the input referred noise is reduced and the phase-margin improved. The enhanced amplifier, simulated in 0.18 μm CMOS technology, exhibits a DC gain enhancement of 16.3 dB as well as 115.5 MHz increase in gain bandwidth compared to conventional FC configuration. The amplifier consumes 360 μW @ 1.2 V which makes it suitable for low-voltage applications.     

A CMOS transconductance amplifier architecture with wide tuningrange for very low frequency applications

A pseudodifferential CMOS operational transconductance amplifier (OTA) with wide tuning range and large input voltage swing has been designed for very small G_M's (of the order of a few nanoamperes per volt). The OTA is based on a modified four-quadrant multiplier architecture with current division. A common-mode feedback circuit structure has been proposed and designed using floating-gate transistors to handle large differential signals. Large on-chip capacitors are emulated through impedance scaling circuits. The circuits, fabricated in a 1.2-μm CMOS process, have been used to design a fourth-order bandpass filter and a relaxation oscillator. Experimental results are in good agreement with the theoretical results     

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

An OTA-based CMOS bandpass filter for NMR applications

One of the very popular medical imaging techniques used in present-day radiology is the magnetic resonance imaging (MRI) which is based on the phenomenon of nuclear magnetic resonance (NMR) in the hydrogen atoms present in the body. There is ever-increasing research in electronic circuit design for biomedical applications using NMR. Earlier magnetic resonance imagers operated at a magnetic field strength of 0.3?T. The present imagers operate at a magnetic field of 1.5?T, the resonance frequency of the nuclei being 64?MHz. This article presents a CMOS bandpass filter (BPF) design for NMR applications. The overall BPF design is realised in 180?nm CMOS technology which occupies an active area of 24.23?×?33.125?µm² and consumes 0.165?mW of power from a 1.5?V supply.     

CMOS current-controlled current differencing transconductance amplifier and applications to analog signal processing

This article presents design of a basic current-mode building block for analog signal processing, named as current-controlled current differencing transconductance amplifier (CCCDTA). Its parasitic resistances at two current input ports can be controlled by an input bias current. Owing to working in current-mode of all terminals, it is very suitable to use in a current-mode signal processing, which is continually more popular than a voltage one. The proposed element is realized in a CMOS technology and is examined the performance through PSPICE simulations. They display usability of the new active element, where the maximum bandwidth is 311 MHz. The CMOS CCCDTA performs low power consumption and tuning over a wide current range. In addition, some examples as a current-mode universal biquad filter, floating inductance simulator and quadrature oscillator are included. They occupy only single CCCDTA.     

Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

一种宽带恒定跨导轨对轨运算放大器的设计

介绍了一种具有轨对轨输入功能的CMOS输入级电路。该电路克服了一般运算放大器只能工作在一定共模输入范围的输入级的缺陷，在各种共模输入电平下有着几乎恒定的跨导，使频率补偿更容易实现，且由于其工作原理与MOS晶体管的C—V解析关系无关，对制造工艺依赖性小，适用于深亚微米工艺。在此基础上，设计出了一种宽带的运算放大器，该运算放大器具有轨对轨输入、输出能力，可以作为常用模拟电路的基本单元模块。它没有严格的共模输入限制，跨导和整体性能稳定，适于为更大规模的数字／模拟混合信号系统提供行为级模型。     

A linear CMOS transconductance element of an adaptively biased source-coupled differential pair using a quadritail cell

A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistor-arrays and discrete components on a breadboard.     

用CMOS跨导单元实现电流模式全极点低通滤波器

提出了用CMOS跨导单元和电容实现电流模式全极点低通滤波器的技术。这一技术基于无源LC梯型电路的模拟，具有电路结构简单、灵敏度低，适合于全集成之特点。     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

A CMOS vector lock-in amplifier for sensor applications

The design of an integrated lock-in amplifier is discussed, specifically conceived for the detection of low-level signals at a harmonic of the drive frequency in magnetically excited resonant structures. The circuit includes in-phase and quadrature analogue signal processing channels, whose outputs feed an integrated ΣΔ analogue to digital converter. The circuit can be operated in different configurations, depending on the application requirements: in particular, by combining the digitized outputs of the two channels, vector operation can be obtained. The entire analogue chain, including the ΣΔ modulator, was designed using fully differential elaboration. The circuit was developed in a , dual poly-Si, four metal layers analogue CMOS technology with high resistivity poly-Si option. Circuit performance is discussed on the basis of transistor-level simulations and measurement results.     

A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications

A CMOS RF digitally programmable gain amplifier (RF PGA), covering various terrestrial mobile digital TV standards (DMB, ISDB-T, and DVB-H) is implemented as a part of a low-IF tuner IC using 0.18-/spl mu/m CMOS technology. An improvement of 13-dB IIP3 is attained without significant degradation of other performance criteria like gain, noise figure, common-mode rejection ratio, etc., at similar power consumption. This is achieved by applying a newly proposed differential circuit gm" (the second derivatives of transconductance) cancellation technique, called the differential multiple gated transistor (DMGTR). In the DMGTR amplifier, the negative value of gm" in the fully differential amplifier can be compensated by the positive value of gm" in the pseudo differential amplifier which is properly sized and biased. By adopting the DMGTR, a low-power highly linear RF PGA is implemented. Also, in order to have wide gain range with fine step resolution, a new RF PGA architecture is proposed. The measurement results of the proposed RF PGA exhibit 50-dB gain range with 0.25-dB resolution, 4.5-dB noise figure, a -4-dBm IIP3 (maximum 30 dBm) and 25-dB gain at 16-mW power consumption.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

A common-gate bootstrapped CMOS rectifier for VHF isolated DC-DC converter

A common-gate bootstrapped CMOS rectifier dedicated for VHF (very high frequency) isolated DC-DC converter is proposed.It uses common-gate bootstrapped technique to compensate the power loss due to the threshold voltage,and to solve the reflux problem in the conventional rectifier circuit.As a result,it improves the power conversion efficiency (PCE) and voltage conversion ratio (VCR).The design saves almost 90% of the area compared to a previously reported double capacitor structure.In addition,we compare the previous rectifier with the proposed common-gate bootstrapped rectifier in the case of the same area;simulation results show that the PCE and VCR of the proposed structure are superior to other structures.The proposed common-gate bootstrapped rectifier was fabricated by using CSMC 0.5 μm BCD process.The measured maximum PCE is 86% and VCR achieves 77% at the operating frequency of 20 MHz.The average PCE is about 79% and average VCR achieves 71% in the frequency range of 30-70 MHz.Measured PCE and VCR have been improved compared to previous results.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

This paper describes a CMOS building block dedicated to high performance mixed analog-digital circuits and systems. The circuit consists of six MOS transistors realizing a new wideband and tunable transconductance. The theory of operation of this device is presented and the effects of transistor nonidealities on the global performances are investigated. Use of the proposed circuit to realize tunable functions (Gm-C filter and current opamp) is illustrated. HSPICE simulations show a wide tuning range of the transconductance value from 40 S to 950 S (500 S) for ±2.5 V (±1.5 V) supply voltages. The transconductance value remains constant up to frequencies beyond 500 MHz. The bandpass filter built with few transconductance blocks and capacitances was simulated with ±2.5 V supply voltage, the center frequency is tunable in the range of 30 MHz to 110 MHz. However, the opamp, which is designed with a transresistance-transconductance architecture, was simulated with ±1.5 V supply voltage. The gain of the opamp can be tuned between 70 dB and 96 dB and high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW. Experimental results on a fabricated transconductor chip are provided.