Multimode $G_{m}$– $C$ Channel Selection Filter for Mobile Applications in 1-V Supply Voltage

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.     

A low-power wide dynamic range envelope detector

We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.     

A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver

A low-IF polyphase channel filter for a dual-mode Bluetooth/Zigbee transceiver is described. Implemented in a standard 0.18-/spl mu/m CMOS process, the filter has a fifth-order 0.5-dB equiripple bandpass response and employs novel transconductor and preamplifier designs. It consumes /spl les/1 mW and achieves image band rejection /spl ges/44 dB, input referred noise of /spl les/52.2 /spl mu/Vrms and input referred third-order intermodulation intercept of /spl ges/20 dBVp, which gives a spurious-free dynamic range of /spl ges/68.4 dB. Chip area including its tuning circuit is 0.23 mm/sup 2/.     

Low-voltage transconductor with high linearity and large bandwidth

A linear tunable CMOS transconductor is proposed which uses a new low-voltage supercascode transistor to provide a high output resistance. Using a standard 0.8 /spl mu/m CMOS technology, simulation results are provided that show the operation of the proposed transconductor with a 1.2 V peak-to-peak differential input signal and 1.5 V supply voltage. The proposed transconductor features a high linearity and more than 100 MHz bandwidth.     

Current-feedback source-degenerated CMOS transconductor with very high linearity

A highly linear current-feedback (CF) transconductor with resistive source-degeneration is developed in CMOS technology. It consists of a differential source follower cascaded with a classical source-degenerated transconductor with its drain current fed back to modulate the bias of the source follower for nonlinearity cancellation, yielding an overall linear transfer function in the circuit. Designed using a 0.35 /spl mu/m CMOS process for a continuous-time delta-sigma application, the CF transconductor achieves a total harmonic distortion better than -80 dB up to 1 MHz for a 0.8 V input differential voltage while the supply voltage is 2.5 V and the power consumption is 3.4 mW.     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

A low-voltage, highly linear voltage-controlled transconductor

A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G/sub m/-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 /spl mu/m/sup 2/ and consumes an average power of 418 /spl mu/w at 125 Mbps and 1.8-V supply.     

1.5 V tunable Square-Root Domain filter

A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 /spl mu/m CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.     

Low-voltage pseudo-differential transconductor with improved tunability-linearity trade-off

A new low-voltage pseudo-differential CMOS transconductor using transistors in the saturation region is presented. It keeps the input common-mode voltage constant, while its transconductance is easily tunable through a DC voltage preserving linearity for a moderate range of G/sub m/ values. Post-layout results for a 2.7 V-0.5 /spl mu/m CMOS design dissipating less than 1.5 mW show a 1:2 G/sub m/ tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 100 /spl mu/A/sub p-p/ differential output.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional low-frequency gain control loop enables the use of an open-loop equalizing filter, which alleviates the speed bottleneck of the conventional adaptation method. In addition, combined adaptation of low-frequency gain and high-frequency boosting improves the adaptation accuracy while supporting high-frequency operation. The open-loop equalizing filter incorporates a merged-path topology and offers infinite input impedance, which are suitable for higher frequency operation and cascaded design. This equalizing filter controls its common-mode output voltage level in a feedforward manner, thereby improving bandwidth. A prototype chip was fabricated in 0.18-/spl mu/m four-metal mixed-mode CMOS technology. The realized active area is 0.48/spl times/0.73 mm/sup 2/. The prototype adaptive equalizer operates up to 3.5 Gb/s over a 15-m RG-58 coaxial cable with 1.8-V supply and dissipates 80 mW. Moreover, the equalizing filter in manual adjustment mode operates up to 5 Gb/s over a 15-m RG-58 coaxial cable.     

Compact power-efficient class-AB CMOS exponential voltage to voltage converter

A novel implementation of a rail-to-rail exponential voltage to voltage converter is presented. It is based on a pseudo-exponential approximation that is easily achieved by the nonlinear currents of a class-AB transconductor. Measurement results for a 0.5 /spl mu/m CMOS technology show a 52 dB output voltage range with linearity error less than /spl plusmn/2 dB using a dual supply voltage of /spl plusmn/750 mV. The power dissipation is less than 40 /spl mu/W.     

A 0.8-V accurately tuned linear continuous-time filter

An accurately tuned low-voltage linear continuous-time filter is presented in this paper. Accurate tuning is achieved using time-constant matched master-slave tuning combined with power-up mismatch calibration. A low-pass biquad designed for a corner frequency of 115 kHz achieves better than -80-dB total harmonic distortion with a 250-mV/sub pp/ 10-kHz input signal. The prototype implemented in 0.18-/spl mu/m CMOS process occupies an area of 0.4 mm/sup 2/ and dissipates 4.6 mW (2.6 mW for the filter and 2 mW for tuning) of power.     

A <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript><Emphasis Type="Italic">-C</Emphasis> continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.     

Switched-current circuits in digital CMOS technology with low charge-injection errors

In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Using a standard logic process, 0.13-/spl mu/m RF CMOS devices with multifinger gate structure have been fabricated. The flicker noise and minimum noise figure characteristics have been investigated with different gate layout splits, where the device parasitic resistance is the determining factor in this issue. The stripe-shaped gate configuration demonstrates better noise performance, due to the reduction of device gate resistance. In addition, the MOS varactors designed with different gate layouts were used in a 5.2-GHz voltage-controlled oscillator (VCO) design, where the VCO with the stripe-shaped (2 /spl mu/m /spl times/ 36 fingers) gate varactor improved about 6 dB in phase-noise performance at 100-kHz offset frequency than that of square-shaped (8 /spl mu/m /spl times/ 9 fingers) gate varactor.     

Current-mode integrator for voltage-controllable low frequency continuous-time filters

A novel differential current-mode integrator (CMI) for voltage-controllable low frequency continuous-time filters is presented. An example fifth-order lowpass filter using the proposed CMI and on-chip capacitors was implemented in an AMI 1.2 /spl mu/m CMOS process, and it achieved -3 dB cutoff frequencies ranging from 160 Hz to 5.6 kHz, by changing a single control voltage.