A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

Effect of Schottky barrier alteration on the low-frequency noise ofInP-based HEMTs

For the first time the effect of increasing the Schottky barrier's Al content of InP-based InAlAs-InGaAs HEMTs from 48 to 60% on the low-frequency (LF) drain and gate current noise is investigated. It is shown that the LF gate current noise S_IG(f) for the 60% case decreases by almost three decades, while the LF drain current noise S _IDS(f) stays at the same level. From small coherence values, it can be concluded that drain and gate noise sources can be treated separately which facilitates the LF noise modeling of these HEMTs     

High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

Experimental and theoretical noise analysis of microwave HEMTs

Low-frequency noise power and high-frequency noise figures in HEMTs (high electron mobility transistors) were measured and compared with calculations based on a one-dimensional noise model to characterize their low-noise properties. It was found that the drain noise current parameter Q in HEMTS is lower than that in GaAs MESFETs. The strong correlation between drain- and induced-gate-noise currents in HEMTs is due to the asymmetric distribution of noise generation along a channel, and the drain noise current is nearly canceled by those induced-gate-noise current. The intrinsic thermal noise from source and gate resistances is about 25% of the total output noise in the 0.25-μm gate-length HEMT considered     

Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

Noise modeling for RF CMOS circuit simulation

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.     

Low-frequency 1/f noise and persistent transients in AlGaN-GaN HFETs

Persistent photoresponse transients and low-frequency 1/f noise were measured in barrier-controlled devices such as AlGaN-GaN heterostructure field-effect transistors (HFETs). The persistent transients and 1/f noise were observed in drain and gate currents. A model describing trapping in a barrier-controlled device introduced, and the appropriate transient evolution and the noise spectra developed. Excellent agreement was obtained between the experimental measurements and the predicted temporal response and noise spectra. Finally, the correlation between drain and gate 1/f noise was measured, confirming that the same noise source (fluctuation in surface potential) is responsible to both currents.     

A novel method for extracting the metallurgical channel length ofMOSFETs using a single device

A new charge-pumping method with dc source/drain biases and specified gate waveforms is proposed to extract the metallurgical channel length of MOSFETs by using a single device. Using two charge-pumping currents of a single nMOSFET measured under different V _GL (V_GH for pMOSFETs), the metallurgical channel length can be easily extracted with an accuracy of 0.02 μm. It is shown that the proposed novel method is self-consistent with the results obtained by the charge-pumping current measured from multidevices under different gate pulse waveforms and bias conditions     

Ultrafast Measurement on NBTI

We combine customary pulsed $I$– $V$ setup with a simple linear drain–current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup. Unlike the ramped-voltage method for which synchronization of the gate and drain waveforms is critical, relative delay between the gate and drain signals is not a concern in our case since measurement is made during quasi-steady state. For the present setup, gate and drain signals are shown to “stabilize” after $sim!hbox{50}$ ns (upon switching) for a gate capacitive load of 1.5 pF (equivalent to $sim!hbox{80} $ devices used in this letter), rendering parallel testing possible using a single gate voltage source. Extension of the method for direct threshold voltage extraction by the constant subthreshold drain current approach is also discussed.      

Noise modeling methodologies in the presence of mobility degradation and their equivalence

For compact modeling of the noise in devices, one of the following three methods is usually applied: 1) An equivalent circuit based approach, 2) the classical Langevin or Klaassen-Prins approach, or 3) the impedance field method. It is well known that for long-channel MOST (where mobility degradation due to a lateral field is absent), all three methods obtain the same result. But it is still not recognized how these methodologies need to be changed when the mobility starts to depend on the electric field. In this work we demonstrate how these methodologies can be adapted to incorporate mobility degradation and show that for any arbitrary mobility model /spl mu/(E) all the methods yield the same expressions for induced gate and drain noise current, which demonstrates the equivalence of the methods. We also present, for the first time, a general expression of induced gate noise which is valid for any mobility model (an expression of the drain current noise was already presented in our previous work) and some very general expressions of noise parameters that can be used for noise modeling with any kind of mobility model.     

Gate flicker noise in MOSFET's

A simple technique for measuring the gate flicker noise component in MOS field-effect transistors (MOSFET's) is presented. The method gives an estimate of the ratio of gate to drain flicker noise currents as compared to the ratio for thermal noise. In addition, the degree of correlation between the gate and drain flicker noise components can be obtained.     

Examination of oxide damage during high-current stress of n-MOStransistors

Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I _d-V_gs characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO₂ interface. It is shown that damage from low drain current stress occurs at the Si-SiO₂ interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO₂ interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO₂ interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO₂ interface at the drain junction edge     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Noise factor contours for field-effect transistors at moderately high frequencies

This analysis of noise behavior is based on an equivalent circuit for the junction field-effect transistor (FET) that was previously published [10]. Since all noise sources in this equivalent circuit are uncorrelated and all significant parasitic elements are already considered, one may apply an easy and direct calculation for the noise factor, which is carried out for the common source, common gate, and common drain configurations. As a result, the constant noise factor contours are represented as circles in the plane of the complex source admittance Y8. This plot of circles is valid above 1/f noise up to moderately high frequencies, and is arrived at by a frequency-dependent normalization of the axis. It is shown that the plot is fully characterized by two frequency-dependent values: the optimum source admittanceY_{8} {opt}and the minimum noise factor Fmin, both being derived from the small-signal equivalent circuit of the FET and the bias condition. The results are in agreement with the commonly held opinion that the noise factor does not differ very much for the three basic configurations [9]. Finally, the theoretical results are verified by measurements at 30 and 60 MHz.     

Optimal noise figure of microwave GaAs MESFET's

The optimal value of the minimum noise figure Foof GaAs MESFET's is expressed in terms of either representative equivalent circuit elements or geometrical and material parameters in simple analytical forms. These expressions are derived on a semiempirical basis. The predicted values of Fofor sample GaAs MESFET's using these expressions are in good agreement with the measured values at microwave frequencies. The expressions are then applied to show design optimization for low-noise devices. This exercise indicates that shortening the gate length and minimizing the parasitic gate and source resistances are essential to lower Fo. Moreover, a simple shortening of the gate length may not bring an improved Founless the unit gate width is accordingly narrowed. The maximum value of the unit gate width is defined as the width above which the gate metallization resistance becomes greater than the source series resistance. Short-gate GaAs MESFET's with optimized designs promise a superior noise performance at microwave frequencies throughKband. The predicted values of Foat 20 GHz, for example, for a half-micrometer gate device and a quarter-micrometer gate device are 3 and 2 dB, respectively. These devices could be fabricated with the current technology.     

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET

In this paper, a drain current model incorporating drain-induced barrier lowering (DIBL) has been developed for Dual Material gate Cylindrical/Surrounding gate MOSFET (DMG CGT/SGT MOSFET) and the expressions for transconductance and drain conductance have been obtained. It is shown that DMG design leads to drain current enhancement and reduced output conductance. The effectiveness of DMG design was scrutinized by comparing with single metal gate (SMG) CGT/SGT MOSFET. Moreover, the effect of technology parameters variations workfunction difference has also been presented in terms of gate bias, drain bias, transconductance and drain conductance. Results reveal that the DMG SGT/CGT devices offer superior characteristics as compared to single material gate CGT/SGT devices. A good agreement between modeled and simulated results has also been obtained thus providing the validity of proposed model.