Superconductor integrated circuit fabrication technology

Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.     

Monte Carlo optimization of superconducting complementary outputswitching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

A 4-bit Josephson computer ETL-JC1

The first computer operation of a 4-b Josephson computer, ETL-JC1 (Electrotechnical Laboratory-Josephson Computer no.1), designed using a reduced instruction set computer (RISC) architecture is described. In the experiment, the computer functions have been verified by executing a computer program installed in a Josephson read-only memory (ROM) at a low repetition frequency. To construct the computer, four Josephson LSI chips including a register and arithmetic logic unit, a sequence control unit, an instruction 1280-b ROM unit, and a 1-kb RAM unit were connected on a nonmagnetic printed circuit board. The Josephson LSI chips were fabricated using Nb/AlO_x/Nb tunnel junctions with 3-μm design rules. The total power dissipation was 6.2 mW in the total circuit, which consists of 22000 junctions including regulators on every chip. On the basis of measurements of the delay times of the logic gates and the access times of the memory chips, it is expected that the program execution in the critical path can be carried out with a single central processing unit in less than 1 ns, resulting in 1 giga-instructions per second (GIPS)     

Optical input/output interface system for Josephson junctionintegrated circuits

An optical input/output interface system for a Josephson junction integrated circuit is fabricated and tested. The system consists of a superconducting optical detector, a dc powered Josephson circuit, a dc powered Josephson high voltage circuit, a liquid-He-cooled semiconductor amplifier, and a liquid-He-cooled semiconductor laser. Features of the system are use of an ultrathin NbN film for the optical detector and adoption of the dc powered Josephson circuits for logic operation circuits. Correct optical output signal is detected by a liquid-He-cooled semiconductor photodiode. The optical input/output interface has the advantage of low heat penetration and low crosstalk compared to the interface using conventional coaxial lines. Moreover, dc powered Josephson circuits have an advantage of low crosstalk from power supply lines compared to conventional Josephson circuits, which are driven by ac supply current     

`Bootstrapping? in Josephson tunnelling logic circuits

`Bootstrapping? in Josephson tunnelling logic circuits has been realised by providing series connection of multiple junctions and feedback of output current as an additional control current. Computer simulations have demonstrated that the speed-up of the circuits is successfully achieved. This configuration is effective for high-fanout logic circuits, memory peripheral circuits, etc.     

Submicron NbN/MgO/NbN Josephson tunnel junctions and theirapplication to the logic circuit

An improved fabrication process for submicron NbN/MgO/NbN Josephson tunnel junctions has been developed. By introducing a contact layer between the junction and the wiring layer, the critical current of the wiring above the junction was considerably enhanced. A logic circuit composed of four-junction logic gates was fabricated using 0.9-μm-square junctions. Logic delay measurement was successfully achieved with a minimum logic delay of 3.6 ps/gate and a wide operating margin of ±17% within 50 gates     

A high-speed four-bit full adder with a resistor coupled Josephson logic

A four-bit full adder circuit implemented in resistor coupled Josephson logic (RCJL) has been designed and successfully tested with 173-ps critical path delay. The full adder circuit uses dual rail logic with emphasis on high-speed operation. An experimental four-bit adder circuit was fabricated using lead-alloy Josephson IC technology with a 5-µm minimum feature size and a 7-µm minimum junction diameter. The circuit consists of 80 devices with 264 junctions. The minimum critical path delay for the ripple carry adder was measured to be 173 ps/4 bits. This result demonstrates the RCJL potential for high-speed digital applications.     

Modeling of a quasi-optical Josephson oscillator

The authors have developed a computer model of a Josephson tunnel junction embedded in a general circuit with frequency-dependent impedance using the harmonic balance method. This model has been applied to the analysis of a two-dimensional Josephson junction array with integrated coupling structures, called a quasi-optical Josephson oscillator. Simulations are done for a junction with dipole, slotline, and bow-tie antennas. The results show that the junction with a bow-tie antenna gives the best performance, and the output power from an array of 4000 junctions can reach 25.7 μW at a frequency as high as 1091 GHz for niobium junctions deposited on a 0.207-mm-thick quartz substrate     

Josephson nonlatching logic circuits

The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.     

An experimental multiplier circuit based on superconducting Josephson devices

This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.     

RSFQ 1024-bit shift register for acquisition memory

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of ±23% and ±14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO_x /Nb process with a junction critical current density of 1.0 kA/cm ²     

Investigation of current–voltage characteristics of vertically stacked all-NbCN Josephson junctions

Current–voltage characteristics of vertically stacked all-NbCN Josephson junctions has been investigated with a purpose to use them as an element of integrated circuits. It has been shown that increases of microwave power in the junction definition process using electron cyclotron resonance (ECR) etching causes reduction of the junction quality parameter. From results of a measurement of current–voltage characteristics for an array composed of five-fold vertically stacked NbCN/MgO/NbCN junctions, it has been found that a very high uniformity in critical currents can be achieved.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 ?W and a signal risetime of approximately 60 ps has been measured.     

Low noise submillimeter SIS receiver with niobium nitride quasiparticle tunnel junctions

We have developed and tested a submillimeter waveguide SIS mixer with NbN-MgO-NbN quasiparticle tunnel junctions. The two junction array is integrated in a full NbN printed circuit. The NbN film critical temperature is 15 K and the junction gap voltage is 5 mV. The size of the junctions is 1.4 × 1.4 µm and Josephson critical current density is about 1.5 KA/cm² resulting in junction R_NωC product about 40. The inductive tuning circuit in NbN is integrated with each junction in two junction array. A single non contacting backshort was tuned at each frequency in the mixer block. At 306 GHz the minimum DSB receiver noise temperature is as low as 230 K. The sources of the receiver noise and of the limits of the NbN SIS submillimeter mixer improvement are discussed.     

Self-biasing Josephson logic circuits

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.     

约瑟夫森阵列振荡器的相位锁定分析

系统地研究了超导亚毫米波阵列振荡器的相位锁定问题。为使超导振荡器达到高工作频率、窄线宽和高稳定的性能，约瑟夫森结与结之间的相位必须相互锁定。相位锁定可以通过结与结之间的耦合电路得以实现。通过对振荡器的各种耦合电路的比较表明，蝴蝶领结天线结构是一个比较适合约瑟夫森振荡器相位锁定的耦合电路。本文提出了一种超导亚毫米波阵列振荡器模型并对其进行了模拟计算与分析，仿真得出了振荡器各项参数值，并给出了相位锁定的条件。     

AC-and DC-powered subnanosecond 1-kbit Josephson cache memorydesign

The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators