Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit

Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film thickness. This study simulates a p-IMOS device on silicon-on-insulator using ATLAS. It is pointed out that the increase of the ratio$L_G/L_ IN$allows a drop of the bias voltage, but involves a degradation of the subthreshold slope. A thin Si film improves the overall device performance. In the second part, the performance of an IMOS-based inverter is investigated, and for the first time an IMOS ring oscillator is simulated.     

Dopingless Impact Ionization MOS (DL-IMOS)- A remedy for complex process flow

We propose a unique approach for realizing dopingless impact ionization MOS (DL-IMOS) based on the charge plasma concept as a remedy for complex process flow. It uses work-function engineering of electrodes to form charge plasma as surrogate doping. This charge plasma induces a uniform p-region in the source side and an n-region in the drain side on intrinsic silicon film with a thickness less than the intrinsic Debye length. DL-IMOS offers a simple fabrication process flow as it avoids the need of ion implantation, photo masking and complicated thermal budget via annealing devices. The lower thermal budget is required for DL-IMOS fabrication enables its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. It is highly immune to process variations, doping control issues and random dopant fluctuations, while retaining the inherent advantages of conventional IMOS. To epitomize the fabrication process flow for the proposed device a virtual fabrication flow is also proposed here. Extensive device simulation of the major device performance metrics such as subthreshold slope, threshold voltage, drain induced current enhancement, and breakdown voltage have been done for a wide range of electrodes work-function. To evaluate the potential applications of the proposed device at circuit level, its mixed mode simulations are also carried out.     

A Novel Depletion-IMOS (DIMOS) Device With Improved Reliability and Reduced Operating Voltage

We experimentally demonstrate a novel depletion-IMOS (DIMOS) device with a 12.1-mV/dec subthreshold slope and 5-decade ON/OFF ratio, employing a depletion mode of operation instead of inversion. DIMOS structure improves reliability by reducing hot carrier injection and features 40% lower breakdown voltages with higher ON currents compared to conventional IMOS.      

RTD的器件模型和模拟——共振隧穿器件讲座(9)

阐述了电路模拟在设计和研制大规模集成过程中的必要性和重要意义,器件模型在电路模拟中的重要性以及器件模拟与器件模型的关系;在器件模拟通用软件形成过程的基础上重点讨论了RTD的器件模型、器件模拟和电路模拟软件SPICE三个课题;介绍了基于物理参数I-V方程RTD模型和高斯函数、指数函数RTD直流模型;利用ATLAS器件模拟通用软件对RTD进行了器件模拟,得到了势垒和势阱宽度、E区掺杂浓度等对RTDI-V特性的影响;以包含RTD电路的SPICE电路模拟中的文字逻辑门为例,通过电路模拟验证了其逻辑功能,对设计该电路起到指导和参考作用。     

Modeling and simulation of hot-carrier-induced device degradationin MOS circuits

The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions     

Physics-based MCT circuit model using the lumped-charge modelingapproach

This paper presents a physics-based model of metal-oxide-semiconductor (MOS) controlled thyristor (MCT) using the lumped-charge modeling technique. As a relatively new power semiconductor device, little effort has been made thus far in creating an accurate model for simulation use. The only MCT model available to date is that using two bipolar transistors-a behavioral subcircuit model. This model works well for static operation, but has limitations in predicting the dynamic behavior of the device due to the omission of the internal device physics. The use of the lumped-charge modeling technique facilitates the inclusion of internal physical processes and the structural geometry of the device into the model. As a result, this technique provides a more realistic and accurate one-dimensional (1-D) model than any other presently available. This paper presents the successful implementation of the lumped-charge approach on hybrid bipolar-MOS power devices such as the MCT. Most importantly, this model is capable of predicting some dynamic soft-switching behavior of the device, which was never realizable by any SPICE-based simulators. The developed model is thoroughly verified through Saber simulation and experimentation     

A semi empirical approach for submicron GaN MESFET using an accurate velocity field relationship for high power applications

A semi empirical model has been proposed for sub-micron GaN MESFET's to calculate the I-V characteristics using an accurate velocity-field relationship obtained by fitting it with the Monte Carlo (MC) simulation. The results so obtained are compared with the experimental results to validate our model and are also compared with the results obtained from the simple saturation model to present the influence of electron drift velocity modeling on the device parameters. The model has been extended to predict the microwave parameters such as transconductance and output conductance of the device.     

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature.In this work,first,the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters.The adjusted parameters are ratio of gate and intrinsic length,gate dielectric thickness and gate work function.Secondly,the DMG (dual material gate) DG-IMOS is proposed and investigated.This DMG DG-IMOS is further optimized to obtain the best possible performance parameters.Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS,shows better ION,ION/IOFF ratio,and RF parameters.Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS,optimized performance is achieved including ION/IoFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm.It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.     

A SPICE modeling technique for GaAs MESFET IC's

A vertically integrated device modeling technique for GaAs IC's is presented for use in circuit simulation. Most of the SPICE2 capability can be utilized for modeling the gate transit time and parasitic effects. A computer program has also been developed to extract model parameters from the measured device data.     

3-D device modeling for SRAM soft-error immunity and tolerance analysis

Soft-error tolerance of static random-access memory (SRAM) devices has been predicted by using three-dimensional (3-D) and time-dependent device simulation in conjunction with circuit simulation. An inverter model developed for 3-D device simulation is described, along with the analysis of the inverters device response as a function of time. The output thus obtained was applied as an input voltage source in circuit simulation of unit SRAM cell and the stability of this bistable circuit is studied on that basis. The effects on soft-error immunity of changes in alpha-particle injection conditions and in load resistance and capacitance are described. The validity of the presented model is examined through comparison of the bit-error-rate dependence on incident angle of alpha particles to that of measured rates. To simulate the angular dependence, we introduce statistical distribution models for alpha-particle energy, position of incidence on the device surface, and angle of incident. Results of device/circuit simulation carried out with many sets of energy, position, and angle are presented. Reasonable agreement between results of simulation and experimental data without the use of adjustment parameters is demonstrated. A map of soft-error tolerance on the CR plane with critical charge Q/sub c/ as a parameter is presented and its derivation explained. An analytic expression for the tolerance is clarified by proposing an equivalent circuit model for the simulation of alpha-particle injection at the output node in an inverter circuit. Inverter modeling is shown to be essential to obtaining SRAM soft-error tolerance to high degrees of accuracy.     

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel.The present model is valid in linear and saturation regions of device operation.The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect.Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated.The model results are validated by numerical simulation results obtained by using the commercially available ATLAS^TM,a two dimensional device simulator from SILVACO.     

Modeling of N-well device and N-well field resistors

Modeling of both N-well device and N-well field is reported here. A simple model as well as an advanced model have been used to model both types of resistors. The modeling has been carried out using MATLAB 6.5 and equations derived from device physics. Detailed modeling of an N-well field resistor, which is not generally available in the literature, has been carried out in great details. The results of various models applicable to different types of N-well resistors have been compared with operating conditions kept the same. A simulation strategy for circuit design has also been suggested.     

Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency

The present work explores the features of gate material engineered (GME) AlGaN/GaN high electron mobility transistor (HEMT) for enhanced carrier transport efficiency (CTE) and suppressed short channel effects (SCEs) using 2-D sub-threshold analysis and device simulation. The model accurately predicts the channel potential, electric field and sub-threshold current for the conventional and GME HEMT, taking into account the effect of work function difference of the two metal gates. This is verified by comparing the model results with the ATLAS simulation results. Further, simulation study has been extended to reflect the wide range of benefits exhibited by GME HEMT for its on-state and analog performance. The simulation results demonstrate that the GME HEMT exhibits much higher on current, lower conductance and higher transconductance as compared to the conventional HEMT due to improved CTE and reduced SCEs. This in turn has a direct bearing on the device figure of merits (FOMs) such as intrinsic gain, device efficiency and early voltage. Tuning of GME HEMT in terms of the relative lengths of the two metal gates, their work function difference and barrier layer thickness has further been carried out to enhance the drive current, transconductance and the device FOMs illustrating the superior performance of GME HEMT for future high-performance high-speed switching, digital and analog applications.     

Numerical simulation and measurement of Gunn device dynamic microwave characteristics

Important characteristics of Gunn devices such as output power, efficiency, and stability are determined by the large-signal dynamic admittance of these devices. Previous attempts to correlate theoretical and measured values in absolute terms for this parameter have met with limited success due to modeling approximations and numerical simulation problems. An improved, implicit numerical simulation scheme has been devised that requires fewer approximations, that gives higher accuracy results with less computational time, and that encounters fewer problems of simulation convergence. For a 10-µm-long GaAs device operating at 10 GHz at a 10-V dc bias, this numerical model predicted results agreeing well with the measured results of device negative conductance that fell from -4.64 to-2.46 mΩ and device capacitance that decreased from 0.701 to 0.691 pF as the RF voltage amplitude increased from 7.72 to 8.71 V. The observed results agreed with the theoretical values to within 6 percent for the negative conductance and to within 15 percent for the device capacitance and represent the best agreement yet achieved between a first principles theoretical model and actual data taken on an oscillating device.     

Modeling of the critical current density of bipolar transistorswith retrograde collector doping profile

Advanced bipolar transistors used for high speed integrated circuits tend to drive high current density. As a result, base-widening occurs and device performance degrades. One of the methods to alleviate the base-widening is to form retrograde collector profiles. In this paper, we have derived for the first time the model of the critical current density of bipolar transistors with retrograde collector profiles. To verify the model, we performed extensively device simulation for two different collector profiles. Results from the model were compared with those of device simulation. The model derived shows a good agreement with device simulation over a V_CB bias range of 1-4 V     

On-line extraction of model parameters of a long buried-channel MOSFET

A buried-channel depletion MOS transistor has an implanted neutral conducting channel between the source and drain due to which the device works in a variety of modes such as accumulation, accumulation-depletion, depletion, inversion-depletion, inversion, etc., and presents a more complex structure than an enhancement-mode device. For precise circuit simulation, accurate and on-line extraction of model parameters has assumed significant importance. It is found that representing the implanted buried channel by an equivalent box with average doping and junction depth gives a convenient trade-off between simplicity in modeling and accuracy in device characterization. The present work proposes a method of deriving the necessary model parameters through the measurement of a single device parameter, namely drain conductance under different operating conditions. The on-line measurements carried on a boron-implanted relatively long buried-channel MOSFET have been used to predict the best box for the profile and give other model parameters necessary for circuit simulation. It is shown that the method is most insensitive to measurement conditions compared to other techniques.     

A new static induction thyristor (SITh) analytical model

In this paper, an analytical static induction thyristor (SITh) model is proposed based on device internal physical operating mechanisms. The nonquasi-static model predicts both device static and dynamic characteristics. The model accounts for effects of the device structure, lifetime, and temperature. Implemented in PSPICE as a subcircuit, model simulation results are compared with numerical simulation and experiment results for various electrical and thermal conditions. The model exhibits accurate results, good convergence, and fast simulation speed     

PMOSFET's热载流子退化模拟及寿命评估的统一模型

对 PMOSFET's几种典型器件参数随应力时间的退化规律进行了深入研究 ,给出了一个新的器件退化监控量 ,并建立了不同器件参数退化的统一模型 .模拟结果和测量结果的比较表明 ,新的退化模型具有较高的准确性和较宽的适用范围 .新的退化模型不但可以用于器件参数退化量的模拟 ,也可以用于器件寿命评估     

A unified physical DC and AC MESFET model for circuit simulation and device modeling

A physically based MESFET model for device modeling and circuit simulation has been developed. The model directly couples the dc and ac models and takes into account velocity saturation as well as the impurity profile as integral parts of the dc and ac models. The model, verified for implanted self-aligned MESFET's, has been implemented in SPICE and used to simulate circuits.