Operating principle of dual collector magnetotransistors studied bytwo-dimensional simulation

Dual collector magnetotransistors are magnetic-field-sensitive devices currently developed in several laboratories. Optimized sensor design is often attempted by trial and error rather than by established design rules. This motivated the present comprehensive study of the operation of magnetotransistors by accurate two-dimensional numerical simulations. We model vertical and lateral transistors as obtained by industrial IC technology on the basis of data provided by the chip manufacturer. We consider the entire device structure with the full, complex device geometry, and the physically proper boundary conditions. Our simulations reveal the details, controversial hitherto, of the operating principle of these devices. In particular we find that, in the case of the vertical transistor, it is essentially the emitter injection modulation effect which dominates the sensor response. In the case of the lateral transistor, the magnetic sensitivity is predominantly determined by minority-carrier deflection, though side effects are involved as well. By variation of the doping profile and the device geometry we derive rules for optimized magnetotransistor design     

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.     

A switching lateral transistor

A switching phenomenon has been reported in certain lateral geometry transistors in silicon integrated circuits. These devices switch between conducting and nonconducting states at a critical value of VCE. A hypothesis for the mechanism has been proposed. In this paper an equivalent circuit is developed for the switching lateral transistor and is used to predict transistor behavior. The effect of manufacturing tolerances on the device switching voltage is investigated and a technique of production control is proposed. Circuits using the device are described in which the circuit switching voltage may be varied over a wide range. Some applications of the switching lateral transistor, as an overvoltage protection circuit and a relaxation oscillator, are described.     

Integrated semiconductor magnetic field sensors

A magnetic field sensor is an entrance transducer that converts a magnetic field into an electronic signal. Semiconductor magnetic field sensors exploit the galvanomagnetic effects due to the Lorentz force on charge carriers. Integrated semiconductor, notably silicon, magnetic field sensors, are manufactured using integrated circuit technologies. Integrated sensors are being increasingly developed for a variety of applications in view of the advantage offered by the integration of the magnetic field sensitive element together with support and signal processing circuitry on the same semiconductor chip. The ultimate goal is to develop a broad range of inexpensive batch-fabricated high-performance sensors interfaced with the rapidly proliferating microprocessor. This review aims at the recent progress in integrated silicon magnetic devices such as integrated Hall plates, magnetic field-effect transistors, vertical and lateral bipolar magnetotransistors, magnetodiodes, and current-domain magnetometers. The current development of integrated magnetic field sensors based on III-V semiconductors is described as well. Bulk Hall-effect devices are also reviewed and serve to define terms of performance reference. Magnetic device modeling and the incorporation of magnetic devices into an integrated circuit offering in situ amplification and compensation of offset and temperature effects are further topics of this paper. Silicon will continue to be aggressively exploited in a variety of magnetic (and other) sensor applications, complementary to its traditional role as integrated circuit material.     

Punchthrough-Voltage Enhancement of AlGaN/GaN HEMTs Using AlGaN Double-Heterojunction Confinement

In this paper, we present an enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility-transistor devices by increasing the electron confinement in the transistor channel using an AlGaN buffer-layer structure. An optimized electron confinement results in a scaling of punchthrough voltage with device geometry and a significantly reduced subthreshold drain leakage current. These beneficial properties are pronounced even further if gate-recess technology is applied for device fabrication. Physical-based device simulations give insight in the respective electronic mechanisms.      

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

The injection model-a structure-oriented model for merged transistor logic (MTL)

The merged transistor device is represented by assigning separate diodes to the various electron and hole injections along the active p-n junction. Where collection takes place, current sources are introduced. Measurement procedures are described that allow a quantitative separation of the various injections, and hence the determination of the model parameters. Results of such measurements are given. Device terminal parameters, like current gains and storage time constants, can be predicted from the measurements for devices of arbitrary horizontal geometry, so that the injection model can serve as a device optimization tool. As a circuit analysis model it allows representation of the internal device series resistances which would not be possible with an Ebers-Moll model. The injection model is significant beyond the merged transistor logic (MTL) aspects as it renders a better insight into bipolar devices, particularly into lateral p-n-p and saturated n-p-n transistors.     

Thermal resistance calculation of AlGaN-GaN devices

We present an original accurate closed-form expression for the thermal resistance of a multifinger AlGaN-GaN high electron-mobility transistor (HEMT) device on a variety of host substrates including SiC, Si, and sapphire, as well as the case of a single-crystal GaN wafer. The model takes into account the thickness of GaN and host substrate layers, the gate pitch, length, width, and thermal conductivity of GaN, and host substrate. The model's validity is verified by comparing it with experimental observations. In addition, the model compares favorably with the results of numerical simulations for many different devices; very close (1%-2%) agreement is observed. Having an analytical expression for the channel temperature is of great importance for designers of power devices and monolithic microwave integrated circuits. In addition, it facilitates a number of investigations that are not practical or possible using time-consuming numerical simulations. The closed-form expression facilitates the concurrent optimization of electrical and thermal properties using standard computer-aided design tools.     

Three-dimensional magnetic-field sensors

Devices sensitive to all three components of a magnetic-field vector are presented. The sensitivity to two field components in the plane of the chip is achieved by merging two one-dimensional vertical magnetotransistors positioned at a 90° angle to each other. An additional surface-collector pair makes this device also sensitive to the last field component, which is perpendicular to the plane of the chip. The sensitivity of the 3-D sensor is represented by a nondiagonal sensitivity-matrix. The smallest achieved sensitive volume is (6×10×16) μm³, which is limited by the design tolerances. The elements of the sensitivity matrix of the device are discussed along with the parameters that influence them. The influence of additional collector pairs on the sensitivity is also discussed. Several 3-D sensitive structures are presented, including magnetotransistor and resistive structures     

Design and simulation of micromechanical thermal converter for RF power sensor microsystem

This paper discusses the thermo-mechanical simulations performed with the aim to optimize the temperature distribution of the microwave power sensor (MPS) microsystem keeping the thermal stress as low as possible. The concept of the absorbed power measurement is based on a thermal conversion, where the dissipated or absorbed RF power is converted into the thermal power, inside a thermally isolated system, so-called the micromechanical thermal converter (MTC) device. A new MTC approach uses a GaAs with an active high electron mobility transistor (HEMT) heater. New technology of low stress polyimide has been used for MTC thermal isolation.By means of thermo-mechanical simulations, we propose a GaAs micromechanical thermal converter design and a layout of the active sensor elements (HEMT heater and a temperature sensor TS) placed on the MTC structure. Spatial temperature distribution, thermal time constant, thermal stress and displacement and the power to temperature characteristics are calculated from the heat distribution. These findings are compared with results of thermo-mechanical measurement of real micromachined MTC devices. The 3-D thermal and thermo-mechanical simulations were performed, using the CoventorWare simulator.     

A compact model for multiterminal bipolar devices used in smartpower applications

Complex technologies merging low-voltage bipolar devices and vertical current-flow power transistor allow more smart functions at low chip cost but pose problems during the design phase because there is no way to predict the influence of the high-voltage transistor over the control components by using standard bipolar junction transistor (BJT) models. In fact the large inductive load usually present in high-voltage power transistors applications forces both negative substrate voltage and spurious currents that can induce positive feedback among parasitic devices, downgrading the performance of a single device and so of the whole circuit. In this work we introduce a model for the five-terminal bipolar devices used in smart power applications. The model accounts for all main static and dynamic parasitic effects and gives results in very good agreement with experimental data on both simple devices and complex integrated circuits currently implemented in commercial products for microprocessor based engine management systems (EMS's)     

Laser annealing of SiGe and Ge based devices

The integration of laser annealing in SiGe and Ge based MOS devices is investigated by means of numerical simulations. Our simulation code is based on two modules: the former simulates the interaction between the laser light and the transistor structure to estimate the heating, the latter simulates heat diffusion, phase changes and material redistribution under irradiation. The model is calibrated in the case of different atomic species (namely Si, Ge and common dopant impurities), considering the thermal properties of the materials and the impurity depending diffusivity in the solid, liquid and interfacial region. We present several simulation results obtained by varying materials, implanted impurity profiles and geometry of the CMOS-like structures. With the support of the simulation results we discuss the possible perspectives of the excimer laser annealing application to the fabrication of post-Si CMOS devices. In particular, we show that by using Ge and SiGe materials the process window for a melting process is larger with respect to the case of traditional Si based devices.     

A quantum-well inversion channel heterostructure as amultifunctional component for optoelectronic integrated circuits

An approach to optoelectronic integration utilizing a universal heterostructure with a single GaAs quantum-well active region is presented. The inversion channel forms the basis of a heterojunction field-effect transistor, a lateral current injection laser, a field-effect modulator, and a waveguide photodetector by simple reconfiguration of the electrodes and device geometry. The fabrication technology has been developed for gigahertz bandwidth applications by utilizing ion implantation techniques for interdevice electrical isolation and surface planarization, and reactive ion-etching to realize a self-aligned transistor-based heterostructure. The design, fabrication, and characterization of various heterostructures are discussed in the context of optoelectronic integration and the implementation of ion implantation disordering to realize low-loss self-aligned waveguides for on chip signal routing. The ultimate performance of the devices using a GaAs quantum well is considered, as well as the development of this technology for improved performance using strained InGaAs wells     

430-V 12.4-$hboxmOmegacdot hboxcm^2$Normally off 4H-SiC Lateral JFET

This letter reports the experimental demonstration of the first 4H-SiC normally off high-voltage lateral junction field-effect transistor. The design and fabrication of such a device have been investigated. The fabricated device has a vertical channel length of 1.8$muhboxm$created by tilted aluminum implantation on the sidewalls of deep trenches and a lateral drift-region length of 5$muhboxm$. Normally off operation$(V_ GS=hbox0 V)$with a blocking voltage$V_ br$of 430 V has been achieved with a specific on-resistance$R_ onhbox- sp$of 12.4$hboxmOmega cdot hboxcm^2$, which is the lowest specific on-resistance for 4H-SiC lateral power switches reported to date, resulting in a$V_ br^2/R_ onhbox- sp$value of 15$hboxMW/cm^2$. This is among the best$V_ br^2/R_ onhbox- sp$figure-of-merit reported to date for 4H-SiC lateral high-voltage devices.     

Impact of the vertical SOI `DELTA' structure on planar devicetechnology

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance     

Device equivalence in integrated optics

The concept of device equivalence is introduced. In equivalent devices, the light propagation can be described by identically evolving modal expansions, resulting in identical power transfer ratios. By first applying this concept to a z-invariant structure with a low refractive-index contrast it is shown how a normalized coordinate space can be defined in which equivalent structures have exactly the same geometry. Subsequently it is shown how this normalized coordinate space can be defined for z-variant integrated optical devices, again provided that the lateral refractive-index contrast is small. This normalization makes it possible to perform numerical device simulations in normalized coordinate space, the results being applicable to a large set of equivalent devices. Furthermore, starting from a known design, it simplifies redesigning that device for use at another wavelength or using other materials significantly, the resulting device being equivalent to the original one