Optimization of Fractional-Order RLC Filters

This paper introduces some generalized fundamentals for fractional-order RL _β C _α circuits as well as a gradient-based optimization technique in the frequency domain. One of the main advantages of the fractional-order design is that it increases the flexibility and degrees of freedom by means of the fractional parameters, which provide new fundamentals and can be used for better interpretation or best fit matching with experimental results. An analysis of the real and imaginary components, the magnitude and phase responses, and the sensitivity must be performed to obtain an optimal design. Also new fundamentals, which do not exist in conventional RLC circuits, are introduced. Using the gradient-based optimization technique with the extra degrees of freedom, several inverse problems in filter design are introduced. The concepts introduced in this paper have been verified by analytical, numerical, and PSpice simulations with different examples, showing a perfect matching.     

Carbon Black based capacitive Fractional Order Element towards a new electronic device

In this paper, Fractional Order Elements (FOEs), fabricated by using a carbon black nano structured dielectrics, are presented. FOEs have been realized by varying different fabrication parameters such as the percentage of carbon black, the curing temperature, and the solvent type.Results on the experimental frequency characterization of one FOE device are given. The FOE has been, then, used for demonstrating the possibility of realizing a fractional order RC filter.The frequency analysis of the RC filter shows the coherence of the fractional order between the FOE and corresponding RC circuit.     

Equivalence of LC and RC oscillators

A general RC oscillator circuit using positive and negative RC elements is derived from a well-known LC oscillator circuit. The active RC network, thus obtained, is shown to represent the equivalent circuits of many existing RC oscillators, such as twin T and Wienbridge oscillators.     

Ramp Input Response of RC Tree Networks

Closed form expressions are presented to accuratelydescribe the delay characteristics of RC tree networks.The Penfield-Rubinstein-Horowitz approach to estimating the stepfunction response of RC trees has been extendedto consider ramp inputs. This result improves timing accuracyby considering the shape of the input waveform driving each individualinterconnect tree while maintaining computational simplicityfor use in the automated timing analysis of complex VLSI circuits.     

Investigation of errors in simulation of devices with distributed parameters

This study deals with the application of the method of transformation functions for investigating the systematic errors in simulation of devices with distributed LC and RC parameters. The specified errors occur while using the traditional techniques. This study also examines the impact of frequency deviation on the values of model transformation functions. In addition, analytical expressions eliminating the systematic errors of simulation of long-distance transmission lines are proposed. The parameter values obtained make it possible to ensure the accurate reproduction of quasi-resonance frequencies of LC and RC phasing networks simulating lines with distributed parameters. A user-friendly interface allowing us, without special training, to carry out investigations of RC networks having arbitrary complexity has been developed.     

Physical implementation of elements with fractal impedance: State of the art and prospects

In this review, we consider elements with a fractal impedance (henceforward, fractal elements, FEs). Advantages and drawbacks of various engineering and technological implementations of FEs are estimated. It is shown that promising FEs appropriate for production and solution of a wide range of scientific and engineering problems are structures on the basis of resistance-capacitance distributed parameter components (RC-DPCs) with the R–C–NR layer structure. It is established that RC-DPC FEs make it possible to implement fractal impedances with complex fractional-power frequency dependence. Examples of physical implementation of RC-DPC FEs are presented.     

Low power,high resolution CMOS variable-delay element

This letter proposes a novel CMOS variable-delay element (VDE). It employs a RC-based differentiator to control the pMOS transistor of a CMOS inverter, whose delay time becomes dependent on the time constant RC. By implementing the RC differentiator with transistor components, the delay can be controlled by variations of both R and C, for fine and coarse delay tuning, respectively. Simulated results show good delay linearity, high resolution and low power consumption for the proposed circuit.     

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

Transient analysis of RC on-chip transmission lines with respect to propagation speed

The effect of finite propagation speed on the total delay through and the transient response of an on-chip transmission line is investigated in the case of an RC line with an open-circuited far end. A model of signal propagation is proposed that enables one to estimate this effect at signal wavefront durations much less than the propagation time. Using analytical formulae derived from the model, the validity range is identified for solutions of telegrapher’s equations as applied to RC interconnections typical of submicrometer technologies.     

Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits

The inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65 nm dual V_t footed domino circuits. Simulations based on 65 and 45 nm BSIM4 models show that the conventional CHIL state (the clock signal is high and inputs are all low) is ineffective for lowering the leakage current and the conventional CHIH state (the clock signal and inputs are all high) is only effective to suppress the leakage current at high temperature other than the high fan-in domino circuits. For the high fan-in footed domino circuits at high temperature and most of footed domino circuits at room temperature, the CLIL (the clock signal and inputs are all low) state is preferable to reduce the leakage current. Further, the influence of the process variations on the leakage current characteristics of the dual V_t footed domino circuits is also evaluated. It is observed that the average leakage current is universally higher than the date reported in the normal corner and the CLIL state is the optimum choice considering the leakage current reduction and the robustness to the process variations simultaneously.     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

Analysis of the dynamics of the local microbreakdown in silicon avalanche photodiode structures

The methods of mathematical simulation are used to study the dynamics of the local microbreak-down in silicon avalanche photodiode structures. The model takes into account the locality of the region of the avalanche multiplication and the delay of the spreading of the avalanche current over the area of the back electrode of the diode. The calculations yield two transient phases of the voltage build-up across the diode: fast (due to the current spreading) and slow (related to the conventional RC recharging). The load resistances needed for the pulsed operation of the avalanche photodiodes are calculated for a series of practically important diode capacitances and spreading resistances of the back electrode.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Fully printed electronics on flexible substrates: High gain amplifiers and DAC

We propose a novel simple Fully-Additive printing process, involving only depositions, for realizing printed electronics circuits/systems on flexible plastic films. This process is Green (non-corrosive chemicals), On-Demand (quick-to-print), Scalable (large-format printing) and Low-Cost vis-à-vis Subtractive printing, a complex deposition-cum-etching process that otherwise requires expensive/sophisticated specialized IC-like facilities and is Un-Green, Not-On-Demand, Un-scalable and High-Cost. The proposed Fully-Additive process features printed transistors with high (∼1.5 cm²/Vs) semiconductor carrier-mobility, ∼3× higher than competing state-of-the-art Fully-Additive processes and comparable to Subtractive processes. Furthermore, passive elements including capacitors, resistors, and inductors, and two metal-interconnect layers are likewise Fully-Additive printed–to our knowledge, to-date the only Fully-Additive process capable of realizing complex circuits/systems on flexible plastic films.Several analog and mixed-signal circuits are demonstrated, including proposed and conventional differential amplifiers, and a charge-redistribution 4-bit digital-to-analog converter (DAC). The proposed amplifier embodies a novel positive-cum-negative feedback to simultaneously significantly improve the gain and reduce susceptibility to process variations. To improve the speed and reduce the area of the DAC, the parasitic capacitors therein are exploited. The Fully-Additive proposed amplifier and DAC are benchmarked against reported realizations (all Subtractive-based processes), and are shown to be highly competitive despite its realization based on the simple low-cost proposed Fully-Additive process.     

Approximate realization of digital fractional forward operator using digital IIR filter

In this paper, a simple and an efficient approach for approximating the digital fractional forward operator z ^m (0?<?m?<?1) using digital infinite impulse response (IIR) filter is proposed. In this method, the coefficients of the closed form digital IIR filter derived for the approximation of the fractional forward operator, in a given frequency band, are based on approximation of fractional order systems. First, analog rational function approximation, in a given frequency band, of the fractional power zero (FPZ) is given. Then, the forward difference generating function is used to obtain a closed form IIR digital filter equivalent of the continuous FPZ, which approximates the digital fractional forward operator. Finally, illustrative examples have been presented to illustrate the effectiveness of the proposed design technique of the fractional forward operator z ^m approximation and its use in performing a fractional m-step prediction.     

A fractional order control strategy for visual servoing systems

In this paper, a control strategy based on fractional calculus for visual servoing systems is proposed. The image-based control strategy is designed using a point features based fractional-order PI controller. A real-time visual servoing system, composed of a manipulator robot with 6 degrees of freedom (d.o.f.) with an eye-in-hand camera, is used for performance evaluation of the proposed control strategy. The image acquisition and processing, together with the computing of the image-based control law are implemented in MATLAB. Using planar static objects, real-time experiments are conducted and the results reveal that the image-based fractional-order PI controller outperforms the conventional image-based integer-order PI controller.     

A 0.5?V high-speed comparator with rail-to-rail input range

A 0.5?V high-speed comparator with rail-to-rail input range is presented. Unlike conventional rail-to-rail comparators that use both NMOS and PMOS input devices, the proposed design takes advantage of zero-V _t NMOS devices that are available in many CMOS processes tailored for analog and mixed signal applications. Design issues associated with the use of zero-V _t devices in comparator circuits are analyzed. Based on a 0.13???m CMOS technology, the proposed design is compared with recently reported sub 1?V comparators and it shows significant performance improvement by the proposed design.     

A quadrature RC-oscillator with capacitive coupling

In this paper the capacitive coupling in quadrature RC-oscillators is investigated. The capacitive coupling has the advantages of being noiseless with a small area penalty and without increasing the power dissipation. The results show that a phase error below 1° and an amplitude mismatch lower than 1% are obtained with a coupling capacitance about 20% of the oscillator׳s capacitance value. Due to this kind of coupling, the phase-noise improves by 3 dB (to −115.1 dBc/Hz @ 10 MHz) and the increase of power requirement is only marginal leading to a figure-of-merit of −154.8 dBc/Hz. This is comparable to the best state-of-the-art RC-oscillators, yet the dissipated power is about four times less. We present calculations of frequency, phase error and amplitude mismatch that are validated by simulations. The theory shows that phase error is proportional to the amplitude mismatch, indicating that an automatic phase error minimization based on the amplitude mismatches is possible. The measurements on a 2.4 GHz voltage-controlled quadrature RC-oscillator with capacitive coupling fabricated in 130 nm CMOS circuit prototypes validate the theory.     

Versatile analog squarer and multiplier free from body effect

This paper proposes the analog CMOS squarer and the four-quadrant analog CMOS multiplier. The major advantages of the proposed circuits are low voltage supply, multifunction of output, and insensitive to the threshold voltage variation caused by body effect. The versatile squarer has two inputs (V _in and I _in ). Its output can be the square of V _in or the square of I _in . The versatile four-quadrant multiplier has four inputs (V _X , I _X , V _Y , and I _Y ). Its output can be the product of V _X and V _Y , the product of I _X and I _Y , the product of V _X and I _Y , or the product of V _Y and I _X . Therefore, the proposed circuits can be applied more than conventional circuits and have good performance. Second-order effects and frequency response are analyzed. Simulation results have verified the workability of the circuits. Experimental results are done to confirm the operation of the circuits.