三值光学计算机中运算请求调度

三值光学计算机具有很多数据位资源使得它能并行处理多个运算请求,因此运算请求的调度就成了三值光学计算机监控系统中不可避免的问题。定义了三值光学计算机中运算请求的四种不同状态,给出了其转换关系;讨论了动态表调度技术,提出了适合三值光学计算机监控系统的运算请求调度策略,如立即调度策略、定时调度策略和基于优先级的先到先服务策略。在此基础上提出了定时调度算法,分析了其特点。在监控系统中实现了该调度算法,并进行了相关实验。实验结果表明该调度算法可行且正确。     

三值光学计算机模拟器的设计与实现

三值光学计算机(ternary optical computer, TOC)作为一种新体系结构的计算机,具有处理器位数众多且易扩展、位功能可重构、位可分组使用等特点,在海量或复杂数据的快速处理方面有很大潜力,但它的应用开发探索尚处于初期。为了扩展其应用范围,提出了一种基于三值光学计算机体系架构的模拟器TOCSim设计方案。该方案通过软件形式模拟TOC的运行过程,并在普通PC机上实现其雏形。TOCSim主要模拟TOC处理器的重构策略、处理器位的分配策略、中间结果解码以及运算效果模拟等过程。通过本模拟器的模拟效果图与TOC原型机上的运行结果光图进行对比,表明该模拟器的设计方案是正确的、可行的。     

一种改进的三值光学计算机MSD无进位加法器的原理与实现

三值光学处理器是三值光学计算机中最重要的器件,人们对此进行了许多研究。目前,基于MSD的三值光学计算机加法器主要是将加数和被加数改写为MSD数,进行T,W变换,再进行丫,W,变换,然后进行T变换,实现无进位加法运算。针对这一种计算方法进行改进,提出了以先进行1', W变换,再进行,T',W'变换,然后进行w'变换的方式进行无进位加法运算的方法。理论和实验证明了此方法的可行性与正确性。通过这种方式,从某种角度看可以减少光学加法器中基元的数量,降低实现的难度,为设计光学加法器提供了的新思路。     

三值光学计算机解码器亮度阈值自动测定技术

为了使三值光学计算机解码器对亮度各不相同的被解码图像都能做到准确解码,提出了根据灰度值对图像像素亮暗判定的阈值设定技术.其基本策略是找出各像素亮状态时的灰度最小值和暗状态时的灰度最大值,以亮状态灰度最小值下移10个灰度级为亮状态的判定阈值,以暗状态灰度最大值上移10个灰度级为暗状态的判定阈值.实验结果表明,以这样的两个阈值为判定标准,三值光学计算机解码器对光学处理器输出结果的判定准确度达到100％.     

基于三值光学处理器的加法算法研究

加法运算是最基本的运算。随着运算数字长度的增加,级联加法器所产生的进位传播导致计算速度的严重下降,学者们提出多种多样的解决方法,其中使用光学方法解决加法进位问题因其并行性独具优势而受到肯定。文中对加法的实现方法进行了分析,并指出简单套用先行进位等算法思想对于三值光计算机不适合,探索适合三值光计算机的光学处理器的加法算法-MSD加法,结合处理器液晶阵列104以上的数据位数,找到更适合三值光计算机特点的加法算法。     

三值光学计算机中MSD加法器的理论和结构

在三值光学计算机中采用MSD加法器,将使这个光学计算机的"三值"和"数据位数众多"两大优势在数值计算中得以充分发挥.以降值设计理论为基础,三值光学计算机既可以随时构造出一个数千位的大加法器来满足计算超大数据的用户,也可以常备一个数据位数适中的加法器来满足普通用户的需要.引入流水计算技术和发明数据剪辑技术后,常备加法器的...     

三值光学计算机中并行MSD整数除法器的设计与实现

除法运算是基本四则运算之一,如何进行快速除法一直是电子计算机、嵌入式系统和其他新型计算系统广受关注的问题.充分发挥三值光学处理器位数众多、运算功能可重构、按位可分配等优势,设计出高效并行MSD(modified signed digit)数除法器对提高大数据除法的运算效率、促进三值光学计算机(ternary optic...     

三值光计算机百位量级编码器的实现

文中给出了使用两块液晶阵列和偏振器实现百位量级三态光编码器的方法。该实验中利用MCS-51系列单片机对两块液晶的控制，实现了百位量级电信号表示的二值信息到百位量级光信号表示的三值信息的转换。实验结果证明了三值光计算机编码器理论的正确性。该编码器为三值光计算机后续部件的研究和实现打下了坚实基础。     

三值光计算机百位量级编码器的实现

文中给出了使用两块液晶阵列和偏振器实现百位量级三态光编码器的方法。该实验中利用MCS-51系列单片机对两块液晶的控制,实现了百位量级电信号表示的二值信息到百位量级光信号表示的三值信息的转换。实验结果证明了三值光计算机编码器理论的正确性。该编码器为三值光计算机后续部件的研究和实现打下了坚实基础。     

基于三值光学计算机的旅行商问题的求解实现*

根据三值光计算机具有的巨并行性特点,对给定城市数的旅行商问题进行研究.首先将旅行商问题进行预处理,并转换为改进的符号数(modified signed-digit,MSD)表示形式;然后根据三值光学计算机的位数众多和MSD加法的无进位过程,建立了相应的计算方法,用自主开发的三值逻辑光处理器系统进行求解.结果表明,在数据...     

三值光计算机半加器结构的简化

半加器是三值光计算机设计中的重要器件,需要尽量设计至最优.通过"剔除光电转换器"有效地简化了半加器结构.该项化简依靠统一设计编码器和半加器来实现,使半加器简化成类似两个液晶阵列和两层偏振片的的叠放.该项化简不仅使半加器的工程实现更容易,而且缩短了半加器的工作周期,从而提高了三值光学计算机完成算术运算的速度.实验结果表明该项化简是成功的.     

Ternary optical computer principle

The fundamental principle and the characteristics of ternary optical computer, using horizontal polarized light, vertical polarized light and no-intensity to express information, are propounded in this paper. The practicability to make key parts of the ternary optical computer from modern micro or integrated optical devices, opto-electronic and electro-photonic elements is discussed. The principle can be applied in three-state optical fiber communication via horizontal and vertical polarized light.     

Principle of a one-step MSD adder for a ternary optical computer

While investigating a three-step MSD adder and the reliability thereof for ternary optical computers(TOC),the principle of one-step MSD addition was found.An important concept,the mid-bit transform,is proposed.Next,the important mid-bit transform table(MTT)for 3-bit MSD input and the corresponding mid-bit transform unit(MTU)are obtained.Using the principle,the concept structure of a one-step MSD adder is proposed such that the sum of the addition can be obtained easily in one step in parallel.By restricting the input symbols,a simplified MTT is obtained and the principle of a one-step adder with restricted input symbols is introduced,together with the corresponding simplified concept structure of a one-step MSD adder.Two examples are presented to demonstrate the principles of one-step MSD adders.This work lays the theoretic foundation for the design of an optical MSD adder in future study.     

Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer

In this paper a new theory referred to as the decrease-radix design （DRD） is proposed, which is found in the research of logic units of ternary （tri-valued） optical computer. Based on the theory proposed, the principles and the regulations of the DRD for making operation units of multi-valued operation with carrying/borrowing free are also presented. The research work has come to the following important conclusion： let D be a special state contained in n physical informative states, then one may figure out any multi-valued processors within n^（n×n） carrying/borrowing free n-valued units by the composition some of n×n×（n-1） simplest basic operating units according to the regulations of DRD proposed in this paper. The detailed systematic way of our design regulations is highlighted step by step in the paper with an example of design of a tri-valued logic optical operating unit. The real architecture, the procedure, and the experimental results of our sample in tri-valued logic operating unit are given. Finally, a re-constructible model of ternary logical optical processor is introduced. The theory proposed in the paper has laid down a solid foundation for the design of re-constructible carrying/borrowing free operating units in ternary optical computers and can be widely used as the designing reference in a variety of multi-valued logic operating units.     

Lane of parallel through carry in ternary optical adder

At the present 50 to 100 microseconds are necessary for a liquid crystal to change its state from opacity to clarity; 1.14×10-5 microseconds are however proved to be enough for light to pass through a clarity liquid crystal device. Rooted from this great difference in time, an optical adder was constructed with parallel through carry lanes (PTCL) composed of liquid crystals. Because all carries in PTCL process in parallel, the carry delay in the ternary optical computer's adder is avoided. Eliminating the carry delay in adder of ternary optical computer by physical means, the PTCL is also applicable for other types of optical adders. Moreover a light diagram of the adder and one PTCL structure are provided.