基于FPGA的FSK加密通信

主要介绍了二进制移频键控FSK通信过程中利用FPGA进行伪随机序列加密的实现方法.移频键控是信息传输中使用较早的一种调制方式,它具有实现容易,抗噪声与抗衰减性能较好的优点,在中低速数据传输中得到了广泛的应用.直接利用FPGA产生伪随机序列的方法可以为系统设计或测试带来极大的便利.给出了基于线性反馈移位寄存器电路,设计一种简洁的伪随机序列发生器的方法.这种方法所产生的随机序列不仅可具有极长的周期,而且还具有良好的随机特性.由于该伪随机序列可以被设计成任意长度,所以设计过程比较灵活.介绍了加密的设计理论、设计过程和硬件实现,该电路可进行下载生成实际电路,并应用到信息安全领域中.     

一种非线性最大长度伪随机序列发生器的设计

伪随机序列在众多领域得到应用,研究伪随机序列的产生具有重要意义.基于m序列,首次提出采用特征函数构造非线性最大长度移位寄存器反馈函数.运用这种方法,构造了一类非线性反馈函数.根据该类反馈函数,设计了非线性伪随机序列发生器,并在FPGA(EPF10K)上得到实现.结果表明,该序列发生器生成的伪随机序列,周期长度,平衡特性、游程特性与m序列相同,非线性度较之得到提高,是难得的序列.     

m序列及其在通信中的应用

介绍了m序列的本原多项式、产生方法及m序列在通信中的应用.m序列的自相关性较好,具有伪随机性,容易产生和复制.主要应用于通信领域中的扩频和加密.频谱的展宽是通过将待传送的信息数据被高速率的伪随机序列(也称扩频序列)调制来实现的,在接收端采用相同的扩频码进行解扩.加密则是利用m序列使信号在携带原始信息的同时具有伪噪声的特点,以达到在信号传输的过程中隐藏信息的目的.     

12×2.5Gbit/s并行伪随机序列发生技术及在线误码块监测

利用FPGA产生并行高速伪随机序列和比特间插奇偶校验8位码误码块的方法实现了在线误码监测。建立了点到点并行高速光传输误码监测实验系统,该系统由12×2.5Gbit/s并行高速伪随机序列发生器、在线误码监测模块、12×2.5Gbit/s并行光接收模块和自制垂直激光阵列发射模块构成,并行光互联采用带宽为400MHz.km5米12芯62.5μm多模带状光纤。     

基于余数系统与置换多项式的高速长周期伪随机序列生成方法

低复杂度长周期数字伪随机序列在现代加密、通信等系统中具有广泛的应用。该文提出一种基于余数系统和有限域置换多项式的伪随机序列生成方法。该方法基于中国剩余定理将多个互质的小周期有限域随机序列进行单射扩展生成长周期数字伪随机序列,置换多项式的迭代计算在多个并行的小动态范围有限域上进行,从而降低了硬件实现中迭代环路的计算位宽,提高了生成速率。该文还给出构建长周期伪随机序列的置换多项式参数选择方法和中国剩余定理优化方法,在现有技术平台下可轻易实现2100以上的序列周期。同时,该方法具有极大的迭代多项式选择自由度,例如仅在q2(mod)3且q503的有限域上满足要求的置换多项式就有10905种。硬件实现结构简单,基于Xilinx XC7Z020芯片实现290的随机序列仅需20个18 kbit的BRAM和少量逻辑资源,无需乘法器,生成速率可达449.236 Mbps。基于NIST的测试表明序列具有良好的随机特性。     

基于乘同余法产生的伪随机序列的区间预测

乘同余法是利用伸长与折叠操作来产生伪随机序列。在此基础上,提出了预测伪随机序列的区间预测方法,该方法不需要确定具体的预测模型,适应范围广,运算速度快。对几种乘同余法产生的伪随机序列实验结果表明,该方法能有效地预测此类伪随机序列,且在一定的信噪比上,预测性能仍然很好。     

谱相关理论用于直接序列扩谱信号的检测与估计

本文论述了谱相关理论在直接序列扩谱信号的检测与估计中的应用，提出了利用谱相关函数法与集平均算法相结合的方法来实现对低信噪比直接序列扩谱信号的检测及其载频与伪码速率的估计，并利用相关处理方法来估计的伪码周期，信息码序列及伪码序列，通过计算机模拟证实了该方法的有效性。     

用于SRAM PUFs的伪随机数发生器的FPGA实现

信息安全问题日益突出,而随机数则是信息安全系统的基石.本文以哈希算法为核心设计了一种伪随机数发生器,其以静态随机存储器物理不可克隆函数（Static Random Access Memory Physical Unclonable Functions,SRAM PUFs）为熵源,能够产生大量的伪随机序列.通过对熵源有效性的在线监测以及对种子的动态重播操作,本文提出的用于SRAM PUFs的伪随机数发生器提高了伪随机序列的安全性,可应用于各种高安全等级加密系统中.该发生器在FPGA开发平台上得到实现,其发生速度达598.1Mbps.随机数检测套件NIST分析结果表明：该伪随机数发生器的输出通过了所有测试项目,具有良好的随机性.     

短码、周期长码直扩信号伪码序列盲估计

针对短码、周期长码直扩信号在不同的时延下伪码序列估计问题,提出了一种基于奇异值分解的盲解扩算法.在已知信息码元速率和伪码周期条件的前提下,算法首先把接收到的直扩信号按照一定长度进行分段构成相关矩阵并对此矩阵进行奇异值分解得出信号子空间,然后根据信号子空间和伪码序列的模糊关系,利用求解的模糊酉矩阵和特定约束条件(如m序列)去其模糊性,最终估计出伪码序列.仿真结果表明,该算法不仅解决了在不同的时延下估计伪码序列带来的问题,而且具有稳定性高、在低信噪比条件下有良好的估计性能等优点.     

基于均匀分布随机数的误码发生器设计

为了模拟信道误码特性,提出了一种基于均匀分布的伪随机误码发生器的设计方法.该方法不用产生高斯分布伪随机数,只需在均匀分布随机数的基础上设置不同的判决门限即可得到不同的误码率,误码率和误码的位置可控.硬件实验表明,该方法比采用高斯随机数的方案节省约96％的资源.     

A micropower low-voltage multiplier with reduced spurious switching

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ~5.6 and ~10 per adder in the adder block in conventional 16times16-bit and 32times32-bit designs respectively to ~2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16times16-bit design dissipates ~32% less power, is ~20% slower but has ~20% better energy-delay-product (EDP) than conventional 16times16-bit multipliers. Our 32times32-bit design is estimated to dissipate ~53% less power, ~29% slower but is ~39% better EDP than the conventional general multiplier     

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm², among which the area of the current-source block is only 0.28 mm². The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.     

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method

We present an automated methodology for producing hardware-based random number generator (RNG) designs for arbitrary distributions using the inverse cumulative distribution function (ICDF). The ICDF is evaluated via piecewise polynomial approximation with a hierarchical segmentation scheme that involves uniform segments and segments with size varying by powers of two which can adapt to local function nonlinearities. Analytical error analysis is used to guarantee accuracy to one unit in the last place (ulp). Compact and efficient RNGs that can reach arbitrary multiples of the standard deviation sigma can be generated. For instance, a Gaussian RNG based on our approach for a Xilinx Virtex-4 XC4VLX100-12 field-programmable gate array produces 16-bit random samples up to 8.2 sigma. It occupies 487 slices, 2 block-RAMs, and 2 DSP-blocks. The design is capable of running at 371 MHz and generates one sample every clock cycle.     

一款32位定点DSP电路的设计

文章通过对32位定点DSP的体系结构及其设计方法的研究,重点阐述了32位定点DSP中CPU包括ALU、MPY、ARAU、流水线、指令系统和总线接口等关键逻辑部件工作原理,对各个逻辑部件的设计思路和实现方法进行了分析描述。采用基于标准单元正向设计方法,设计了一款32位指令集的定点DSP电路,该电路采用哈佛总线结构,可以在单周期内实现16×16位有符号整数乘法、32位累加和32位数据的算术逻辑运算,处理精度高。该电路采用0.5μm 1P3M CMOS工艺流片,集成度7万门,工作频率可达36 MHz,动态功耗594 mW。     

Method for generating pseudo random numbers based on cellular neural network

To overcome the degradation characteristics of chaos system due to finite precision effect and improve the sta-tistical performance of the random number,a new method based on 6th-order cellular neural network (CNN) was given to construct a 64-bit pseudo random number generation (PRNG).In the method,the input and output data in every iteration of 6th-order CNN were controlled to improved the performance of the random number affected by chaos degradation.Then the data were XORed with a variable parameter and the random sequences generated by a Logistic map,by which the repeat of generated sequences was avoided,and the period of output sequences and the key space were expended.Be-sides,the new method was easy to be realized in the software and could generate 64 bit random numbers every time,thus has a high generating efficiency.Test results show that the generated random numbers can pass the statistical test suite NIST SP800-22 completely and thus has good randomness.The method can be applied in secure communication and other fields of information security.     

Boolean-chaos-based physical random number generator

A novel method for generating physical random numbers using Boolean-chaos as the entropy source was proposed.An autonomous Boolean network (ABN) without self-feedback was constructed by using two-input logic gates,and its dynamic characteristics were analyzed.Based on this,a 15-node ABN circuit was implemented to successfully generate Boolean-chaos with a bandwidth of ~680 MHz and a min-entropy around 1.By implementing the entropy source and the entropy extraction circuit on a single FPGA,the physical random number generation with a real-time rate of 100 Mbit/s was finally achieved.The NIST SP800-22 and DIEHARD randomness test results demonstrate that the obtained random sequences by the method successfully pass all tests.This indicates the random numbers has good random statistical characteristics.     

Design of a 16 384-bit serial charge-coupled memory device

This paper describes a 16 384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil²/bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 µs.     

一种基于FPGA实现的真随机数发生器

本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。电路为纯数字形式,50MHz采样时钟采得的输出数据可以无需后处理,直接通过随机性测试,且未发现随机性与采样频率存在显著联系。     

Fast generation of prime numbers and secure public-key cryptographic parameters

A very efficient recursive algorithm for generating nearly random provable primes is presented. The expected time for generating a prime is only slightly greater than the expected time required for generating a pseudoprime of the same size that passes the Miller-Rabin test for only one base. Therefore our algorithm is even faster than algorithms presently used for generating only pseudoprimes because several Miller-Rabin tests with independent bases must be applied for achieving a sufficient confidence level. Heuristic arguments suggest that the generated primes are close to uniformly distributed over the set of primes in the specified interval.Security constraints on the prime parameters of certain cryptographic systems are discussed, and in particular a detailed analysis of the iterated encryption attack on the RSA public-key cryptosystem is presented. The prime-generation algorithm can easily be modified to generate nearly random primes or RSA-moduli that satisfy these security constraints. Further results described in this paper include an analysis of the optimal upper bound for trial division in the Miller-Rabin test as well as an analysis of the distribution of the number of bits of the smaller prime factor of a random k-bit RSA-modulus, given a security bound on the size of the two primes.Some results of this paper were presented at EUROCRYPT '89, Houthalen, Belgium, April 10–13, 1989 [55].