类脑神经网络与神经形态器件及其电路综述

为了系统地了解类脑神经网络电路,在对类脑神经网络进行简要介绍的基础之上,重点阐述两种类别的神经形态器件及功能,包括不同类型的浮栅管和不同工艺材料的忆阻器来模拟单个神经元和突触可塑性功能;然后,以神经形态器件为基础,分别介绍了基于浮栅管和忆阻器实现神经网络电路;最后总结当前神经形态器件及类脑神经网络芯片存在的问题,并对有关类脑计算研究方向进行了展望.     

Reduction 93.7% time and power consumption using a memristor-based imprecise gradient update algorithm

The conventional computing system with the architecture of von Neumann has greatly benefited our humans for past decades, while it is also suffered from low efficiency due to the separation between a memory block and a processing unit. Memristor, which is an emerging electron device with the capability of data storage and processing information simultaneously, can be employed to construct a bioinspired neuromorphic computing system. Simulation as one of the most powerful methods to obtain the optimizing result for the memristor-based neuromorphic network has been extensively focused to realize the high precision calculation. It becomes very difficult because the pulse-to-pulse (P2P) model is limited by the updating process. The memristor-based multi-layer Perceptron (MLP) network online training generally presents a low accuracy. Therefore, an efficiency training schedual is urgently desired to improve the accuracy. Based on the resistive switching behavior observed in the Ag/TiOx/F-doped SnO₂ memristor, the weight update by the P2P model enables the MLP network online training in the low accuracy memristor with high performance. The low bits MLP optimized by a novel weight update schedual can realize high precision identification and classification. By that, the time and power consumption of memristor can be largely reduced. The experiment result illustrates that the high accuracy of 90.82% and 95.44% can be obtained at the first and final epoch of the MNIST handwritten digital datasets, respectively. Importantly, the number of the weight update, and the online training time and power consumption can be reduced by 81% and 93.7%, respectively. The scheme provides high precision, low power consumption, and fast convergence solution for the in-situ training of the imprecise memristor-based neuromorphic network.

     

Flexible memristor based neuromorphic system for implementing multi-layer neural network algorithms

Abstract

This paper describes a memristor-based neuromorphic system that can be used for ex situ training of various multi-layer neural network algorithms. This system is based on an analogue neuron circuit that is capable of performing an accurate dot product calculation. The presented ex situ programming technique can be used to map many key neural algorithms directly onto the grid of resistances in a memristor crossbar. Using this weight-to-crossbar mapping approach along with the memristor based circuit architecture, complex neural algorithms can be easily implemented using this system. Some existing memristor based circuits provide an approximated dot product based on conductance summation, but neuron outputs are not directly correlated to the numerical values obtained in a traditional software approach. To show the effectiveness and versatility of this circuit, two different powerful neural networks were simulated. These include a Restricted Boltzmann Machine for character recognition and a Multilayer Perceptron trained to perform Sobel edge detection. Following these simulations, an analysis was presented that shows how both memristor accuracy and neuron circuit gain relates to output error.     

Choosing Between Two Classification Learning Algorithms Based on Calibrated Balanced $$5\times 2$$ Cross-Validated F-Test

Ion-channel variability has critical effect on the spike initiation and propagation in nervous system. Noise can play a constructive role leading to increased reliability or regularity of neuronal firing and spike propagation in the nervous system. In this paper we show that memristors can be considered as an electronic analogous of the Hodgkin–Huxley ion channels not only in terms of threshold switching effect but also in terms of stochastic behavior. In other words, memristor can also implement stochastic version of Hodgkin–Huxley equation. Switching effect in memristive devices is thermodynamically driven, which is stochastic in nature. We show that if the intrinsic stochastic behavior of memristor is taken into account, memristor based neuristor can also implement stochastic version of Hodgkin–Huxley axon model in generation of action potential. Ion channel variability in neurons can be modeled by intrinsic stochastic behavior of memristor. We incorporate noise in the memristor model by adding white Gaussian noise to the deterministic part of dynamical state evolution function of the memristor. We study the reliability of spike timing for spike train generated by memristor based neuristor in which the noise included memristor model is used. Also, the reliability of spike propagation along thin axons is discussed. A series connection of neuristors can be used as an axon in which neuristor acts as a node of Ranvier on an axon. Probabilistic nature of spike propagation on thin axons can be modeled using neuristor in which the variability nature of memristor is included.     

忆阻器阻变机制及其材料研究进展

忆阻器可以将信息存储和逻辑运算整合到一个电子器件上,这将打破传统的冯·诺依曼计算机架构,其应用前景不可估量.首先简述了忆阻器的发展历程及其基本概念;其次综述了忆阻器的阻变机制及其材料的选择,将目前已知的阻变机制主要概括为3类,即阴离子阻变机制、阳离子阻变机制和纯电子机制,同时详细叙述了不同类型材料在忆阻器应用中的特点;...     

Multi-input volistor logic XNOR gates

ABSTRACT

A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology – the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power.

Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S ₁ and S ₂ through horizontal wires W _in1 and W _in2, and the output which is logical AND of states S ₁ and S ₂ is calculated by applying V _READ to vertical wire W _XNOR. (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches.     

Thermodynamic-RAM technology stack

Abstract

We introduce a technology stack or specification describing the multiple levels of abstraction and specialisation needed to implement a neuromorphic processor (NPU) based on the previously-described concept of AHaH Computing and integrate it into today’s digital computing systems. The general purpose NPU implementation described here is called Thermodynamic-RAM (kT-RAM) and is just one of many possible architectures, each with varying advantages and trade offs. Bringing us closer to brain-like neural computation, kT-RAM will provide a general-purpose adaptive hardware resource to existing computing platforms enabling fast and low-power machine learning capabilities that are currently hampered by the separation of memory and processing, a.k.a the von Neumann bottleneck. Because understanding such a processor based on non-traditional principles can be difficult, by presenting the various levels of the stack from the bottom up, layer by layer, explaining kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM, instruction set, sparse spike encoding, kT-RAM emulator, and SENSE server.     

Bayesian neural network enhancing reliability against conductance drift for memristor neural networks

The hardware implementation of neural networks based on memristor crossbar array provides a promising paradigm for neuromorphic computing.However,the existence ...     

Design of Hopfield network for cryptographic application by spintronic memristors

Memory being one of the essential credential in today’s computer world seeks forward newer research interests in its types. Hopfield neural networks of artificial neural networks are one of its classes that can be modelled to form an associative memory. In this paper, we have shown the Hopfield neural network constructed with spintronic memristor bridges accounting to act as an associative memory unit. The memristors are nanoscaled, in terms of size, which possess synaptic behaviour in the artificial neuromorphic system. The associative behaviour is realised by the updation of synaptic weights of memristive Hopfield with single- and multiple-bit associativity which is simulated in MATLAB. The application of the hardware in the field of cryptography is also proposed.

     

Analog memristive memory with applications in audio signal processing

Since the development of the HP memristor, much attention has been paid to studies of memris- tive devices and applications, particularly memristor-based nonvolatile semiconductor memory. Owing to its unique properties, theoretically, one could restart a memristor-based computer immediately without the need for reloading the data. Further, current memories are mainly binary and can store only ones and zeros, whereas memristors have multilevel states, which means a single memristor unit can replace many binary transistors and realize higher-density memory. It is believed that memristors can also implement analog storage besides binary and multilevel information memory. In this paper, an implementation scheme for analog memristive memory is considered. A charge-controlled memristor model is derived and the corresponding SPICE model is constructed. Special write and read operations are demonstrated through numerical analysis and circuit simulations. In addition, an audio analog record/play system using a memristor crossbar array is designed. This system can provide great storage capacity （long recording time） and high audio quality with a simple small circuit structure. A series of computer simulations and analyses verify the effectiveness of the proposed scheme.     

Expanded HP memristor model and simulation in STDP learning

Based on the classical HP memristor found by HP Lab, this paper presents an expanded model that making fully consideration of the influence of R _on, that is, R _on is the similar order of magnitude of R _off. Simulations proved that in some particular conditions, the hysteresis effect of the expanded model is the same as HP memristor. A comparison was made between these two models under some given conditions. Then, we built several simulations to test the classical characteristics of the expanded HP memristor. Simulation results demonstrate that the expanded model is superior to the original in some aspects like easy switching and power saving. At last, we applied the expanded HP memristor in STDP learning simulation, which shows it is a good candidate for neural network when a threshold voltage function is proposed.     

Multistability of periodic delayed recurrent neural network with memristors

This paper discusses the recurrent neural network (RNN) with memristors as connection weights. Memristor is a nonlinear resistor. Memristance varies periodically with time when the sinusoidal voltage source is applied. According to this property of memristor, it shows that coefficients of RNN with memristors are periodic functions with respect to time t. By dividing the state space and using contraction mapping theorem, one sufficient condition is obtained for multiperiodicity. And the periodic orbits located in saturation regions are locally exponentially stable limit cycles. At last, one example is given for verifying the validity of our result.     

Trends of deposition and patterning techniques of TiO2 for memristor based bio-sensing applications

Memristor is a new element that has potential in various fields such as memory, neural network, FPGA, computing and bio-sensing. Among listed, research on memristor in bio-sensing applications is very minimal. There are a lot of researches done in bio-sensing applications but they are not looking at the memristive behavior effect but most of them are looking at surface effect or cyclic voltammetry effect or amperometric response. This study will focused on memristive behavior of memristor sensor in bio-sensing applications. At first, this paper discusses brief overview about deposition techniques of TiO₂. In second part, the details overview of TiO₂ patterning techniques will be covered. There are four patterning techniques that can be used for TiO₂ patterning which are lift off techniques, sol–gel base imprint lithography techniques, etching techniques and site-selective deposition techniques. Third part discussed in general about bio-sensing applications including two researches on memristor sensor that has been done. At last, this paper will propose a design of memristor sensor using TiO₂ material to be used in bio-sensing applications. TiO₂ material was chosen as the sensing material due to its wide used in sensing applications including gas sensing, bio-sensing and humidity sensing. TiO₂ is also the best material that has the best memristive behavior beside Si, ZnO and others.     

A programmable ternary CPU using hybrid CMOS/memristor circuits

Abstract

The carry propagation of arithmetic operations is one of the major shortcomings of common binary number encodings as the two’s complement. Signed-digit arithmetic allows the addition of two numbers without carry propagation and in asymptotically constant time in dependence of the word length, while at the same time requiring a digit representation with more than two states. With the advent of memristors, it has become possible to store multiple states within a single memory cell. This paper proposes an implementation of a general purpose CPU using signed-digit arithmetic by exploiting memristors in order to implement multi-value registers. The proposed model of the CPU is evaluated by the execution of various image processing algorithms. It is shown that a break-even point exists at which signed-digit algorithms outperform conventional binary arithmetic operations. Furthermore, simulation results prove that the memristor device lends itself to store signed-digit data efficiently.     

基于自选尾数压缩的高能效浮点忆阻存内处理系统

矩阵向量乘法(matrix-vector multiplication,MVM)运算是高性能科学线性系统求解的重要计算内核.Feinberg等人最近的工作提出了将高精度浮点数部署在忆阻阵列上的方法,显示出其在加速科学MVM运算方面的巨大潜力.由于科学计算不同类型的应用对于求解精度的要求各不相同,为具体应用提供合适的计算...     

基于忆阻器的计算存储融合体系结构研究进展

Memristor is an enabling device with non volatile resistance, low power consumption, high durability, ease of integration, and CMOS compatibility. The stateful logic of memristors can rea lize the true fusion of computing and storage, and is complete in logic, which is expected to break the limitation of Von Neumann architecture and effectively alleviate the memory wall bottleneck. These excellent properties gain memristors great interest from academia and industry. In light of this, this paper summarizes the research progress of application oriented computing storage fusion architecture based on stateful logic. Firstly, the implementation principle and improvement method of state logic are analyzed in detail. Secondly, the state logic design based on the memristor crossbar is reviewed, including the parallel implementation of the basic logics, copy operation and comparison operation, and then the design principle and implementation structure of the data storage structure based on the memristors are summarized. The paper then revisits an application oriented computing storage fusion architecture in detail, and finally summarizes the problems in the research of this direction, and looks forward to the future direction.     

Assessing alternative technologies for the cost-effective computation of derivatives

One should not separate the method of computing the expected present value of a derivative from its ultimate computing topology. In the following sections we discuss the cost benefit is sues involved with implementing several methods for computing derivative statistics on alter nate computing topologies. We show how the choice of topology impacts the computing time for a particular example of a time consuming derivative valuation. We conclude by showing how all these factors can be represented as a case based expert system which can be used to help an organization assess its computing alternatives.     

多媒体技术研究:2015——类脑计算的研究进展与发展趋势

目的 类脑计算,是指仿真、模拟和借鉴大脑神经网络结构和信息处理过程的装置、模型和方法,其目标是制造类脑计算机和类脑智能。方法 类脑计算相关研究已经有20多年的历史,本文从模拟生物神经元和神经突触的神经形态器件、神经网络芯片、类脑计算模型与应用等方面对国内外研究进展和面临的挑战进行介绍,并对未来的发展趋势进行展望。结果 与经典人工智能符号主义、连接主义、行为主义以及机器学习的统计主义这些技术路线不同,类脑计算采取仿真主义：结构层次模仿脑（非冯·诺依曼体系结构）,器件层次逼近脑（模拟神经元和神经突触的神经形态器件）,智能层次超越脑（主要靠自主学习训练而不是人工编程）。结论 目前类脑计算离工业界实际应用还有较大差距,这也为研究者提供了重要研究方向与机遇。     

忆阻器状态逻辑中与操作的高效设计与实现

作为电阻、电容、电感之外的第4种基本电路元件,忆阻器自2008年被发现以来受到学术界和产业界的广泛关注.忆阻器的阻值记忆效应和纳米工艺制造方式使其被认为可用于构建未来更大容量和密度的存储器,逐渐替代FLASH等现有存储器件.除存储功能外,HP公司在2010年《Nature》上发表的文章表明,忆阻器还可以通过以蕴含为基础的状态逻辑实现任意逻辑运算.研究了忆阻器状态逻辑的另一种操作——与操作,提出了一种更加高效的与操作实现方法,该方法不需要增加额外的忆阻器,降低了激励电压的复杂性,减小了误差,使运算更加简便高效.最后通过SPICE模拟仿真对提出的方法进行了验证.