A novel clocking technique for VLSI circuit testability

Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these requirements for certain designs with static flip-flops that are controlled by two independent signals (master clock and slave clock). This is possible because, in normal circuit operation, the master and slave clocks are never simultaneously active. The new clocking structure uses the `all clocks active' condition to specify the scan mode. Implementation of the concept is discussed in detail for two-clock circuits. Single-clock circuits can be modified to use this scheme, and the results for this class of design are also presented.     

VLSI system design for automotive control

Presents a novel VLSI approach for combustion engine control. The approach is based on a real-time solution of a thermodynamical differential equation. The control system calculates an optimum ignition point by fast measurement and real-time processing of signals as temperature, pressure, and volume of the combustion chamber. The required computational power cannot be met with standard signal processors. The design of a mechatronic system that is based on an application-specific vector architecture is presented. Each design step from the analysis of the heat release algorithm, the optimization of the algorithm and the dataform, the mapping on architecture, the physical design of the testchip set and the single chip, the chip test, and the system integration, is presented. Finally, the application at an engine test-stand and results are shown.<>     

Capacitance coefficients for VLSI multilevel metallization lines

The problem of reducing the complexity of parasitic capacitance evaluation of interconnection lines in a multilevel stratified dielectric medium (a good approximation for VLSI) is considered. We start out with a review of the Green's function method for the Si-SiO2composite and its derivation via the Fourier integral approach. Next, a piecewise linear finite-element technique is proposed to solve the integral equations that relate charges to potentials and lead to the desired capacitance matrix. We show by example that the proposed method is both less complex than methods based on piecewise constant surface charge distributions and equally accurate. This supports the accuracy and usefulness of the technique for IC design.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

In-situ testability design (ISTD)—A new approach for testing high-speed LSI/VLSI logic

After a discussion of the main problems encountered in conventional methods used for testing high-speed LSI/VLSI logic, a new approach, to be called the "in-situ testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability-that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

Analog/digital ASIC design for testability

The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the problems associated with testing basic circuit configurations for different types of commonly used analog macros. Using the recommended architecture to gain access to control and observation test points in the analog portions of the mixed analog/digital ASIC, a series of analog test tables for several different analog functions have been derived. The analog test procedures are independent of any digital design for testability that might be used in the digital portions of the ASIC. General testing procedures for current analog/digital ASICs are described along with desirable characteristics for testers for this type of circuit     

The economics of scan-path design for testability

In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.     

Analytical thermal model for multilevel VLSI interconnectsincorporating via effect

The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k_ILD,eff, with k _ILD,_eff=k_ILDη/, where η is a physical correction factor, with 0<η<1. Both the spatial temperature profile along the metal lines and their average temperature rise can be easily obtained using these models. The predicted temperature profiles are shown to be in excellent agreement with the three-dimensional (3-D) finite element thermal simulation results. The model is then applied to estimate the temperature rise of densely packed multilevel interconnects. It is shown that for multilevel interconnect arrays, via density along the lines can significantly affect the temperature rise of such interconnect structures     

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

A VLSI design for a trace-back Viterbi decoder

A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods     

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.     

Parallel VLSI design for a real-time video-impulse noise-reduction processor

High-quality televisions (TVs) such as improved digital TV, enhanced TV, and high-definition TV have become popular in recent years. However, impulse noise affects TV broadcasts. This paper proposes an efficient noise-removal algorithm using an adaptive digital signal-processing approach. Simulations have demonstrated that the new adaptive algorithm could efficiently reduce impulse noise even in highly corrupted images. In order to achieve real-time implementation, a cost-effective architecture is proposed using a parallel structure and pipelined processing. The proposed processor can achieve the throughput rate of 45M pixels/s using only 4k gates and two line buffers. Unlike median-filtering chips, this processor provides better filtering quality and its circuit is much less complex.     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.     

VLSI: linking design and manufacturing

A set of computer-aided design (CAD) tools that predict the effects of various manufacturing steps along with the chip's internal dimensions is described. Called the Process Engineer's Workbench, the system predicts the chip's characteristics, their statistical distribution, and the manufacturing yield likely from any one fabrication process. The tools are even sensitive to the small random variations that increase in significance as devices shrink in size. Workbench can be used to compare its programs' predictions and those of other software tools with actual measurements of devices and processes. Some existing CAD tools are reviewed to highlight the Workbench's advantages, and the features of the latter are examined. Written in C language for a Digital Equipment VAXstation, Workbench was designed to be portable and runs on several other popular workstations. It contains two basic libraries, namely, one of device models, the other of process step models