A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals

A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-/spl mu/m pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm/sup 2/ and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board.     

An 80/20-MHz 160-mW multimedia processor integrated with embeddedDRAM, MPEG-4 accelerator and 3-D rendering engine for mobileapplications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-μm embedded memory logic (EML) technology. Its area is 84 mm², and power consumption is 160 mW when all of the functions are activated     

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.     

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm×10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% of that for the conventional CMOS design     

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.     

Design methodology of embedded DRAM with virtual-socketarchitecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-μm design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT     

A 7.1-GB/s low-power rendering engine in 2-D array-embedded memorylogic CMOS for portable multimedia system

A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm² prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 V operation, is demonstrated with a host PC through a PCI bridge     

Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256×16×128 to 2 K×16×256 (Word×Bit×Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations     

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.     

Impact of three-dimensional transistor on the pattern area reduction for ULSI

The impact of three-dimensional transistors, double-gate transistor, trench-isolated transistor (TIS) (using sidewall gate)/FinFET, and surrounding gate transistor (SGT) on the pattern area reduction for ultra-large-scale integration (ULSI) has been described. The pattern area of the gate logic, such as NAND or NOR, with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 47, 48%, respectively, compared with the conventional planar case using the same feature size, F. The pattern area of the tapered buffer circuit with the double-gate transistor, TIS/FinFET or SGT can be reduced to 58, 20, 48%, respectively. These three-dimensional transistors can be adapted to ULSI such as application specific integrated circuit (ASIC), microprocessor (MPU), dynamic random access memory (DRAM), and embedded DRAM. The smallest pattern area may be realized with TIS/FinFET or SGT of 47-48% for ASIC, with TIS/FinFET of 42% for MPU, with SGT of 65% for DRAM and with TIS/FinFET or SGT for embedded DRAM. For designing the circuit with TIS/FinFET the design of the trench depth (2F for gate logic, 12F for tapered buffer) is the key issue. The design of the cell library for SGT is a task for the future.     

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators

Enabled by the emerging three-dimensional (3D) integration technologies, 3D integrated computing platforms that stack high-density DRAM die(s) with a logic circuit die appear to be attractive for memory-hungry applications such as multimedia signal processing. This paper considers the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. In this work, we develop one specific DRAM organization and image frame storage strategy geared to motion estimation. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency. With a DRAM performance modeling/estimation tool and ASIC design at 65 nm, we demonstrate the energy efficiency of such 3D integrated motion estimation accelerators with a case study on HDTV multi-frame motion estimation.     

Dynamically shift-switched dataline redundancy suitable for DRAMmacro with wide data bus

A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-μm technology     

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficientredundancy and enhanced testability

This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm ² and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm² and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

A 1.0-V 230-MHz column access embedded DRAM for portable MPEGapplications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm² and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented     

An 8-ns random cycle embedded RAM macro with dual-port interleavedDRAM architecture (D2RAM)

A novel fast random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²RAM) has been developed. The macro exploits three key circuit techniques: dual-port interleaved DRAM architecture, two-stage pipelined circuit operation, and write before sensing. Random cycle time of 8 ns under worst-case conditions has been confirmed with a 0.25-μm embedded DRAM test chip. This is six times faster than conventional DRAM     

A compact thermal noise model for the investigation of soft errorrates in MOS VLSI digital circuits

A compact VLSI MOSFET model that includes an integrated thermal noise model and a methodology for the analysis of the effects of thermal noise on the performance and error rates of digital integrated circuits is presented. The usefulness of the model and methodology is demonstrated by comparing simulation results for signal-to-noise ratio to analytic results for the balanced bit-line architecture of the single-device DRAM and the associated cross-coupled pair sense amplifier. The design options and tradeoffs related to thermal noise are introduced for both the balanced bit lines and the sense amplifier are considered. The error rate as a function of signal-to-noise ratio is determined, and possible limits to DRAM construction due to inherent thermal noise are highlighted     

A statistical methodology as applied to a 256 Mbit DRAM passtransistor design

We present a novel design for manufacturing (DFM) methodology that has been applied to the design of a pass transistor for 256 Mbit DRAM. The design inputs that include gate oxide thickness, which limits the booted wordline voltage, the threshold voltage adjust implant, and the substrate bias voltage, for different channel lengths, are optimized to meet the constraints on performance, reliability, and robustness against manufacturing variations. The problems associated with applying conventional DFM techniques are discussed and a new methodology based on “margins” is presented. The results pertaining to the optimized DRAM pass transistor design for a power supply voltage V_cc=2.5 V are presented,     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown