The Equivalence of Reliability Diagrams and Fault-Tree Analysis

Many practicing engineers model their systems using reliability diagrams, while others use fault-tree analysis. The theoretical equivalence of the two techniques is described. System reliability can be expressed in two ways: probability of success and probability of failure approach, in terms of the tie-sets (forward paths) of a reliability diagram. Similarly, one can write two other expressions in terms of the cut-sets of the system reliability diagram. If one uses the fault-tree analysis approach, the probability of failure is written in terms of element failures by applying the rules of symbolic logic (union and intersection). This equation is identical with the tie-set probability of failure equation. Also by applying DeMorgan's logic theorem to the fault-tree probability of the failure equation, one obtains the tie-set probability of success equation. Thus the two techniques are shown to be identical. The choice between the techniques is a matter of convenience and familiarity.     

Case study: reliability of the INEL-Site Power System

Recent power outages at the EG&G Idaho National Engineering Laboratory (INEL) prompted some customers to call for major modifications to the power system. The reliability of the INEL-Site Power System (a loop configuration) was analyzed to understand the true performance of the system and the dominant causes of outages. This was done using fault-tree modeling along with the IRRAS-PC computer code. Twenty-nine years of site-specific data were obtained from logbooks maintained by the INEL-Site Power System dispatch office. A detailed model was developed and validated against outage history for the site. The fault-tree analysis identified several major contributors to the outage frequency. It is shown that the fault-tree analysis technique provides a flexible and useful method for quantifying the system unreliability and identifying the major contributions to it. The model accurately describes the overall, INEL-Site Power System (INEL-SPS) performance and can easily be used to quantify the anticipated change in reliability due to potential modifications in the system     

A model for system reliability with common-cause failures

A model for the analysis of systems subject to common-cause failures is proposed. The system consists of a finite number of components that are subject to: (1) statistically independent failures, and (2) external failure causes (they need not be mutually statistically independent) for groups of components. Applications to fault-tree analysis and network reliability problems are discussed     

Fault Tree Analysis, Methods, and Applications?A Review

This paper reviews and classifies fault-tree analysis methods developed since 1960 for system safety and reliability. Fault-tree analysis is a useful analytic tool for the reliability and safety of complex systems. The literature on fault-tree analysis is, for the most part, scattered through conference proceedings and company reports. We have classified the literature according to system definition, fault-tree construction, qualitative evaluation, quantitative evaluation, and available computer codes for fault-tree analysis.     

Dependability analysis of systems with on-demand and active failuremodes, using dynamic fault trees

Safety systems and protection systems can experience two phases of operation (standby and active); an accurate dependability analysis must combine an analysis of both phases. The standby mode can last for a long time, during which the safety system is periodically tested and maintained. Once a demand occurs, the safety system must operate successfully for the length of demand. The failure characteristics of the system are different in the two phases, and the system can fail in two ways: (1) it can fail to start (fail on-demand), or (2) it can fail while in active mode. Failure on demand requires an availability analysis of components (typically electromechanical components) which are required to start or support the safety system. These support components are usually maintained periodically while not in active use. Active failure refers to the failure while running (once started) of the active components of the safety system. These active components can be fault tolerant and use spares or other forms of redundancy, but are not maintainable while in use. The approach, in this paper, automatically combines the "availability analysis of the system in standby mode" with the "reliability analysis of the system in its active mode." The general approach uses an availability analysis of the standby phase to determine the initial state probabilities for a Markov model of the demand phase. A detailed method is presented in terms of a dynamic fault-tree model. A new "dynamic fault-tree construct" captures the dependency of the demand-components on the support systems, which are required to detect the demand or to start the demand system. The method is discussed using a single example sprinkler system and then applied to a more complete system taken from the off-shore industry     

Boolean Difference Techniques for Time-Sequence and Common-Cause Analysis of Fault-Trees

Fault trees are a major model for the analysis of system reliability. In particular, Boolean difference methods applied to fault trees provide a widely used measure of subsystem criticality. This paper generalizes the fault-tree model to time-varying systems and uses timedependent Boolean differences to analyze such systems. In particular, suitable partial Boolean differences provide maximal and minimal solution sets for sensitization conditions. A method of common-cause failure analysis based on partial time-dependent Boolean differences allows the study of failures due to repeated occurrences, at different times, of the same phenomenon. Such methods generalize to systems with repair, and under certain assumptions of independence, steady-state distributions can be used for the analysis of system faults. These methods are generally useful in reliability and sensitivity analysis.     

Fault-tree analysis for system design, development, modification,and verification

A methodology that uses fault-tree analysis (FTA) techniques to assess the weaknesses of a new chemical/process design at any time during system development is presented. FTA provides a cost-effective means of improving or verifying the reliability and efficiency of chemical/process design. It evaluates the consequences of conceivable failure to indicate where improvements are justified. FTA techniques were used to model the failure modes of an existing control-room heating, ventilation, and air-conditioning (HVAC) system of a large production facility. The fault-tree reduction revealed 129 single-, 434 double-, and 442 triple-failure combinations, any of which could cause system failure. Single failures and double failures consisting of an equipment malfunction and an operator failure error were targeted for design and/or procedural modifications. These modifications were then incorporated into the operating system design to enhance system availability. In an iterative fashion, FTA techniques were reapplied to the modified design and used to verify the adequacy of the proposed revisions prior to implementation. This resulted in a thorough review of system vulnerabilities and a clear understanding of how to correct them     

Using intuitionistic fuzzy sets for fault-tree analysis on printed circuit board assembly

Fault-tree analysis (FTA) is a powerful technique used to identify the root causes of undesired event in system failure by constructing a tree of sub-events, spreading into bottom events, procreating the fault and finally heading to the top event. From integrating expert’s knowledge and experience in terms of providing the possibilities of failure of bottom events, an algorithm of the intuitionistic fuzzy fault-tree analysis is proposed in this paper to calculate fault interval of system components and to find the most critical system component for the managerial decision-making based on some basic definitions. The proposed method is applied for the failure analysis problem of printed circuit board assembly (PCBA) to generate the PCBA fault-tree, fault-tree nodes, then directly compute the intuitionistic fuzzy fault-tree interval, traditional reliability, and the intuitionistic fuzzy reliability interval. The result of this proposed method is compared with the existing approaches of fault-tree methods.     

Approximate sensitivity analysis for acyclic Markov reliability models

Acyclic Markov chains are frequently used for reliability analysis of nonmaintained mission-critical computer-based systems. Since traditional sensitivity (or importance) analysis using Markov chains can be computationally expensive, an approximate approach is presented which is easy to compute and which performs quite well in test cases. This approach is presented in terms of a Markov chain which is used for solving a dynamic fault-tree, but the approach applies to any acyclic Markov reliability model.     

Synthesis of Fault Trees: An Example of Noncoherence

The Lapp & Powers (L&P) fault-tree model of a nitric acid cooling process is explored to a greater level of depth than in the previous round-robin correspondence on the controversy over exclusive-or (XOR) gate G7 in the L&P fault tree. In this paper, the minimalized logic equations for success or failure of G7 are derived, and the subsystem reliability function is calculated. The subsystem reliability vs component reliability function is U-shaped; this is not an abnormality, but a result of the XOR failure logic. The overall system reliability vs component reliability function, however, is J-shaped. Some further comments are made on the relevance of this problem to the study of s-noncoherent and fail-safe systems.     

Dynamic fault-tree models for fault-tolerant computer systems

Reliability analysis of fault-tolerant computer systems for critical applications is complicated by several factors. Systems designed to achieve high levels of reliability frequently employ high levels of redundancy, dynamic redundancy management, and complex fault and error recovery techniques. This paper describes dynamic fault-tree modeling techniques for handling these difficulties. Three advanced fault-tolerant computer systems are described: a fault-tolerant parallel processor, a mission avionics system, and a fault-tolerant hypercube. Fault-tree models for their analysis are presented. HARP (Hybrid Automated Reliability Predictor) is a software package developed at Duke University and NASA Langley Research Center that can solve those fault-tree models     

Fault-tree analysis: a knowledge-engineering approach

This paper deals with the application of knowledge engineering and a methodology for the assessment and measurement of reliability, availability, maintainability, and safety of industrial systems using fault-tree representation. Object oriented structures, production rules representing the expert's heuristics, algorithms, and database structures are the basic elements of the system. The blackboard architecture of the system supports qualitative and quantitative evaluation of the fault tree. A fuzzy set approach analyzes problems with few failure data or much fuzziness or imprecision. Fault-tree analysis is a knowledge acquisition structure that has been extensively explored by knowledge engineers. Reliability engineers can apply the techniques developed by this area of computer science to: (1) improve the data acquisition process; (2) explore the benefits of object oriented expert systems for reliability applications; (3) integrate the several sources of knowledge into a unique system; (4) explore the approximate reasoning to handle uncertainty; and (5) develop hybrid solution strategies combining expert heuristics, conventional procedures, and available failure data     

System reliability analysis of an N-version programming application

This paper presents a quantitative reliability analysis of a system designed to tolerate both hardware and software faults. The system achieves integrated fault tolerance by implementing N-version programming (NVP) on redundant hardware. The system analysis considers unrelated software faults, related software faults, transient hardware faults, permanent hardware faults, and imperfect coverage. The overall model is Markov in which the states of the Markov chain represent the long-term evolution of the system-structure. For each operational configuration, a fault-tree model captures the effects of software faults and transient hardware faults on the task computation. The software fault model is parameterized using experimental data associated with a recent implementation of an NVP system using the current design paradigm. The hardware model is parameterized by considering typical failure rates associated with hardware faults and coverage parameters. The authors results show that it is important to consider both hardware and software faults in the reliability analysis of an NVP system, since these estimates vary with time. Moreover, the function for error detection and recovery is extremely important to fault-tolerant software. Several orders of magnitude reduction in system unreliability can be observed if this function is provided promptly     

FPGA-based Monte Carlo simulation for fault tree analysis

The reliability analysis of critical systems is often performed using fault-tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computations. This is because an extremely large number of simulated samples may be needed to estimate the reliability parameters at a high level of confidence.In this paper, a tree model, called Time-to-Failure tree, has been presented, which can be used to accelerate the Monte Carlo simulation of fault trees. The time-to-failure tree of a system shows the relationship between the time to failure of the system and the times to failures of its components. Static and dynamic fault trees can be easily transformed into time-to-failure trees. Each time-to-failure tree can be implemented as a pipelined digital circuit, which can be synthesized to a field programmable gate array (FPGA). In this way, Monte Carlo simulation can be significantly accelerated. The performance analysis of the method shows that the speed-up grows with the size of the fault trees. Experimental results for some benchmark fault trees show that this method can be about 471 times faster than software-based Monte Carlo simulation.     

On Multistate System Analysis

Discrete function theory, which extends switching function theory and multiple-valued logic function theory, is introduced into multistate system analysis. Some theoretical conclusions and algorithms which play key roles in multistate system analysis are presented. The concepts of s-coherence and duality in binary-state system analysis are generalized. The set of minimal upper (maximum lower) vectors for level j, which play the role of min path (cut) set, is introduced to represent the states of a monotonic multistate system. Two approaches to computing state probability of multistate systems are given, one is based on inclusion-exclusion, the other is based on enumeration. Binary-state fault-tree is extended to multistate fault-tree. A computer code (MSTA1) has been programmed and is used to evaluate a multistate fault-tree. Multistate fault-tree and the computer code have been applied to paper-making industry; the results are consistent with the field data.     

A Reliability Model for Error Correcting Memory Systems

This paper evaluates the reliability of a memory system incorporating any sort of linear error-correcting code. If the failure hypothesis is too simple (viz, a failure affects the entire memory chip or only one memory bit) an evaluation of reliability can be wrong. The following considerations are thus important: 1. The failure model is based on the internal design of the memory chip. 2. The memory system hardware is accurately accounted for. The resulting model is very close to the hardware implementation and depends on six parameters. The model is very useful for easily comparing memory systems and for deriving tradeoffs among the implementation possibilities for the design of memory systems.     

MB-OFDM UWB系统中交织器盲识别方法

借助峰值平均功率比(PAR)与反转误码率(RSER)信息,实现MB-OFDM UWB系统在发送端选择最佳交织器后,在不传送交织辅助信息情况下,在接收端恢复发送端使用的交织器编号,实现交织过程盲识别。将反转误码率的检测应用到对交织器的盲识别中,改进MB-OFDM UWB系统中的交织器与解交织器部分,通过对反转误码率的比较识别出发送端所选择的交织器规格,进而达到对交织序列的盲识别。对常规与改进后的系统进行误比特率仿真比较后,发现改进后的MB-OFDM UWB系统具有较好的可靠性,可以通过反转误码率的比较信息得出交织器编号,进而得到交织序列,释放信道,达到真正意义上的交织盲识别,从而实现智能通信。     

Qualitative Analysis in Reliability & Safety Studies

The qualitative evaluation of system logic models is described as it pertains to assessing the reliability and safety characteristics of nuclear systems. Qualitative analysis of system logic models, i.e., models couched in an event (Boolean) algebra, is defined, and the advantages inherent in qualitative analysis are explained. Certain qualitative procedures that were developed as a part of fault-tree analysis are presented for illustration. Five fault-tree analysis computer-programs that contain a qualitative procedure for determining minimal cut sets are surveyed. For each program (SETS, MOCUS, PREP, MICSUP, ELRAFT), the minimal cut-set algorithm and limitations on its use are described. The recently developed common-cause analysis for studying the effect of common-causes of failure on system behavior is explained. This qualitative procedure does not require altering the fault tree, but does use minimal cut sets from the fault tree as part of its input. The method is applied using two different computer programs, COMCAN and SETS.     

PSM: an object-oriented synthesis approach to multiprocessor systemdesign

Although multiprocessor systems are becoming a trend today, few synthesis tools currently available can actually automate the design of multiprocessor systems. Performance synthesis methodology (PSM) is an object-oriented system-level synthesis approach to multiprocessor system design. Since PSM was designed specifically for the synthesis of multiprocessor systems, it is not only much more efficient when synthesizing parallel systems, but also produces better parallel systems than currently available uniprocessor system-level synthesis tools. Colored Petri nets used in modeling system components and object modeling technique used in the design process have both contributed to the shortening of system development time and to the reduction of design cost. First, user specification consisting of functional models and performance constraints is translated into architecture models. Then, the system is configured by selecting the method of control, the memory organization, the type of processor, and the type of system interconnection. Finally, a heuristic design space exploration algorithm is used to generate several near-optimal design alternatives. The best architecture is chosen by evaluating the design alternatives using a flexible performance estimation formula that mainly considers system level design features, such as system throughput, utilization, reliability, scalability, fault-tolerance, and cost. Several systems were successfully synthesized using this top-down object-oriented PSM, thus showing its feasibility as a design automation tool for parallel systems