New ESD challenges in RFID manufacturing

The introduction of dual-band RFIDs (Radio Frequency Identification Devices) in chip cards created new ESD risks with unconventional discharge paths. On a plastic foil, a more or less grounded coil antenna for radio frequency (RF) is aluminium-printed on one half of the card. On the other half, an electrical floating, but thus, highly electrostatic charged folded dipole for ultrahigh frequency (UHF) is arranged. When the chip is placed by a flip-chip assembly process, a strong discharge takes place through the RF-UHF-path of the chip. Usual ESD protective structures are only of limited use in these cases. Discharge paths and specific risks are described in this paper as well as useful countermeasures in foil and assembly processes.     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

The layout dependence on ESD robustness of NMOS and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the energy band diagrams.     

电镀双极化现象浅析

主要论述了电镀过程中的双极化现象及阐明其发生机理,并据此提出避免双极化的措施。     

TFT-LCD摩擦工艺ESD研究与改善

摩擦工艺ESD(Electrostatic Discharge)是TFT-LCD制程中较为常见的一种不良,以317.5 mm(12.5 in)产品为例,摩擦工艺过程中ESD发生率20%,对产品良率影响较大。文章结合实际生产对摩擦工艺ESD的原因进行理论分析与实验验证,得出摩擦工艺发生ESD的原因为TFT基板上面有悬空的大块金属,在摩擦过程中电荷积累过多容易发生ESD,ESD进一步烧毁旁边金属电路导致面板点亮时画面异常。生产过程中通过工艺管控和产品设计两方面优化改善,工艺方面通过增加湿度,涂布防静电液以及管控摩擦布寿命进行改善,设计方面通过变更悬空的大块金属为小块金属,通过工艺设计优化最终生产过程中摩擦工艺ESD发生率由20%下降到0%,大大提高了产品品质,降低了生产成本。     

Optimizing the controller IC for micro HDD process based on Taguchi methods

The future trend of controller integrated circuit (IC) for micro hard disk driver (HDD) is to be lighter, thinner, shorter and smaller. The storage capacity and unit cost of micro HDD is lower than of flash memory card. The optimal packaging manufacturing process for driver IC for micro HDD is Chip Scale Package (CSP). However, the production and assemble process for CSP is much more difficult. Especially, the warpage problem on modeling results in non-conforming products. This research is to discover the optimal production levels for control factors based on the orthogonal array in Tachugi method. The product size used in the study is the driver IC package overall height less than 0.65 mm for micro HDD with CSP manufacturing process.     

深亚微米工艺ESD电路设计参数研究

通过器件级仿真来评估ESD保护器件的鲁棒性的方法,对ESD电路的关键设计参数进行了研究.通过器件仿真软件MEDICI对栅极到源极接触孔的距离,栅极到漏极接触孔的距离以及栅极的宽度和长度对ESD性能的影响进行了研究,并分析了它们的失效机理.从而得出经验公式,可以在流片前估算出器件的ESD失效电压.通过在设计阶段预测器件的ESD性能可以缩短设计周期,节约成本.     

灭菌剂在PCB制造中的应用与研究

介绍了一种灭菌剂在PCB电镀制程中的应用情况,通过实验数据得出,其对改善因水质问题引起的板面铜渣、铜丝等不良现象有明显的效果,同时对改善生产线的水质和节省用水量也有一定的作用。它对PCBT的产品品质、成本节约和环保等方面均具有积极的意义,具有良好的推广价值。     

Circuit and process design considerations for ESD protection in advanced CMOS processes

This paper reviews many of the important issues for building ESD protection with NMOS transistors containing silicided diffusions and lightly doped drain junctions. The impact of device process parameters, such as gate length, side-wall spacer and silicided, graded junctions, on NMOS ESD performance are discussed. More recent process advances, such as LATID and halo implants, are also reviewed. Several varieties of circuits for triggering NMOS protection transistors under ESD conditions are covered.     

Statistical process control in semiconductor manufacturing

This paper summarizes the basic concepts and tools of Statistical Process Control as used today in semiconductor manufacturing. After their introduction, important concepts are illustrated with the help of application examples drawn from the area of yield control, photolithography and plasma etching. Time series modeling and the impact of computer integrated manufacturing will also be discussed.     

Modeling of the silicon integrated-circuit design and manufacturing process

The evolution of process modeling is traced starting with bipolar technology in the 1960's through recent processing concerns for oxide-isolated MOS devices. The kinetics of diffusion and oxidation are used to illustrate both physical and numerical effects. The interaction of device effects with process modeling is discussed as well as the statistical implications of process variables. The nature of computer-aided design tools for process and device modeling are discussed. This includes tools that bridge gaps between technology and system design with potential application for manufacturing.     

Statistical process control in semiconductor manufacturing

The author presents a brief survey of standard SPC (statistical process control) schemes, and illustrates them through examples taken from the semiconductor industry. These methods range from contamination control to the monitoring of continuous process parameters. It is noted that, even as SPC is transforming IC production, the peculiarities of semiconductor manufacturing technology are transforming SPC. Therefore, the author describes novel SPC applications which are now emerging in semiconductor production. These methods are being developed to monitor the short production runs that are characteristic of flexible manufacturing. Additional SPC techniques suitable for in situ multivariate sensor readings are also discussed     

Stimulated phenomena in the surface Cherenkov process byunmagnetized electron beam

The operability of the surface Cherenkov laser with unmagnetized electron beam is considered. The small-signal gain of the surface Cherenkov laser for various regimes is calculated. The dependence of the gain on the electron beam angular spread is analyzed. The quantum mechanical consideration shows the possibility of the electron-beam quantum modulation after the interaction     

关于机械制造工艺可靠性的研究

由于机械制造业这是我国第二重要性产业,机械制造业应该存在各个方面积极配合,这项工作复杂而且存在系统性,我国机械制造对比发达国家起步比较晚,面临着比较落后的技术,与国际制造业发展水平比较难跟上。混乱管理机制与短期机械研制时间,这也就导致我国长期存在比较多水平发展的机械制造水平与特别缓慢的发展速度。针对这样的情况,通过研究分析我国机械制造业与强化机械制造工艺可靠性研究存在十分重要的意义。     

Technology design for high current and ESD robustness in a deepsubmicron CMOS process

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 μm and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity     

Influence of parasitic structures on the ESD performance of a pure bipolar process

The purpose of this work is to show that parasitic structures greatly affect the ESD performance of a bipolar process. More especially, the existence of a parasitic diode in parallel to the protection transistor in the input stages of a pure bipolar IC leads to a low ESD performance for HBM stresses, while the ESD performance for MM stresses is high. Suppression of this diode significantly increases the ESD performance for both types of stresses.     

二阶HDI板工艺流程开发

主要讨论二阶HDI板的工艺开发流程,以实验的方式确定其关键制程的设置并对实验过程中遇到的一些问题进行讨论。     

Fuzzy assignment of manufacturing process tolerances

The assignment of process tolerances is vital to the success of production, therefore, a systematic and reliable approach should be developed to assist the process planner in designing the tolerances. Conventional methods assign tolerances without considering the process capability of machinery, as a result, the tolerances allocated may not agreeable economically. This study proposes a new formulation to concurrently maximize the standardized process tolerances; the original multiobjective programming is consolidated into a single objective problem by using the fuzzy technique. Comparison results with other methods indicate that the presented model can design process tolerances by generating the least overall scrap rate     

浅谈电子制造过程中的静电及静电防护

静电释放（ESD）就是一定数量的电荷从一个物体（例如人体）传送到另一个物体（例如芯片）的过程。这个过程能导致在极短的时间内有一个非常高的电流通过芯片,35％以上的芯片损坏都可以归咎于此。因此,在电子制造行业里保护芯片免受静电释放的损害是非常重要的。实际上,很多企业在各种不同电子应用中都遇到了如何应对急速增长的静电防护需求的问题。文章针对ESD机制和防护做了一个较全面的介绍,包括ESD原理、电流产生、危害、防静电工艺要求等。     

Yield learning and the sources of profitability in semiconductor manufacturing and process development

A numerical model that identifies the high-leverage variables associated with profitability in semiconductor manufacturing is presented. Varying the parameters of the model demonstrates that a rapid yield-learning rate determines profitability more than any other factor does. Factors such as ramping-up early, adding fab capacity, depressing the terminal fault density, and shrinking die size all yield diminishing returns. The model also suggests that developing a rapid problem-solving capability in the early stages of process development enables successful yield learning.