Emerging SiGe HBT reliability issues for mixed-signal circuit applications

We review the emerging reliability issues associated with high-performance SiGe HBT technologies which are being increasingly deployed in a wide variety of mixed-signal circuit applications. For the purposes of this work, we define the concept of device "reliability" to be broader than its standard usage in the industry, to include all possible transistor degradation mechanisms, for all possible mixed-signal circuit designs, in any of the various intended mixed-signal applications. For instance, in addition to classical device reliability mechanisms associated with reverse emitter-base and high forward current density stress, new reliability issues for SiGe HBTs, including impact-ionization induced "mixed-mode" stress, scaling-induced breakdown voltage compression and operating point instabilities, geometrical scaling-induced low-frequency noise variations, and the impact of ionizing radiation on device and circuit reliability, are also addressed.     

Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices

Automotive and telecom applications often require voltages in the 20-30 V range. These circuits combine high-performance CMOS with a high-voltage MOS transistor. A possible choice for the high-voltage device is an n-channel lateral DMOS (NLDMOS) transistor. An advantage of an NLDMOS transistor is that it can be easily integrated within existing technologies without significant process changes. In most cases, though, the drain drift implant must be optimized to meet safe operating area (SOA) and hot carrier (HC) reliability requirements. This paper focuses on understanding anomalous SOA and HC results obtained from an NLDMOS transistor whose drain drift implant dose was varied     

A Regional Approach for Computer-Aided Transistor Design

A regional approach to transistor design is presented which makes possible the determination of transistor gain hFE for any transistor (doping profile specified) operating at any given values of emitter current IE and collector-to-emitter voltage VCE. This approach extends the classical diffusion theory of transistors to include conductivity modulation, voltage-controlled base motion, and current-controlled base motion (base widening). Due to the simplicity of this technique, time-sharing computer techniques were used. This allowed for user interaction, making this approach very attractive for education as well as design. The regional approach is a likely candidate for satisfying the needs for the device designer (it contains device performance versus doping profile), the circuit designer (it allows determination of equivalent circuit models from knowledge of the electron and hole densities throughout the device), and the academic world (it is simple and physical). It is anticipated that the regional approach will allow engineers to develop a "feel" for transistor behavior under wide ranges of operating conditions.     

Application of Transistor Emitter-Open Turn-Off Scheme to High Voltage Power Inverters

A transistor emitter-open turn-off scheme has been implemented in an experimental operating high voltage power inverter. Not only the transistor turn-off speed is greatly increased by using such a turn-off scheme but also the reverse-biased second breakdown phenomenon is eliminated. Therefore the very same device can be fully utilized for higher voltage and higher frequency applications.     

Safe operating area of GaAs MESFET for nonlinear applications

This paper provides a new approach to evaluate the transistor safe operating area for a nonlinear operation in the overdrive operating conditions. This approach has been implemented for a MESFET technology. The methodology consists in performing ON-state and OFF-state accelerated DC step stresses for bias conditions, which can be reached by V/sub DS/ and V/sub GS/ sweeps in the overdrive operating conditions. Hence, the results of an RF ageing test performed in nonlinear conditions have confirmed the methodology used in this paper.     

Degradation state analysis of the IGBT module based on apparent junction temperature

The multi-chip parallel insulated gate bipolar transistor (IGBT) is the core device in large-capacity power electronic equipment, but its operational reliability is of considerable concern to industry. The application of IGBT online degradation state analysis technology can be benefcial to the improvement of system reliability. The failure mechanism of IGBT devices is discussed in this paper, and a technique for analyzing the degradation state of IGBT based on apparent junction temperature is proposed. First, the distortion consistency of the voltage rise time in various failures is discussed, and the junction temperature dependence of the voltage rise time is then demonstrated. Subsequently, an apparent junction temperature model based on the voltage rise time is established (the ftting accuracy is as high as 94.3%). From the high-frequency model in the switching process of the device, an online extraction technology of key parameters (e.g., voltage rise time) is developed. Finally, an experimental platform for IGBT degradation state estimation is established, and the feasibility of IGBT degradation state estimation based on apparent junction temperature is proved, especially the degradation of bonding-wire and the gate-oxide-layer. The experimental results show that the proposed IGBT degradation state estimation technique based on apparent junction temperature is a reliable online estimation method with non-contact, high accuracy, and comprehensiveness.     

Degradation state analysis of the IGBT module based on apparent junction temperature

The multi-chip parallel insulated gate bipolar transistor (IGBT) is the core device in large-capacity power electronic equipment, but its operational reliability is of considerable concern to industry. The application of IGBT online degradation state analysis technology can be benefcial to the improvement of system reliability. The failure mechanism of IGBT devices is discussed in this paper, and a technique for analyzing the degradation state of IGBT based on apparent junction temperature is proposed. First, the distortion consistency of the voltage rise time in various failures is discussed, and the junction temperature dependence of the voltage rise time is then demonstrated. Subsequently, an apparent junction temperature model based on the voltage rise time is established (the ftting accuracy is as high as 94.3%). From the high-frequency model in the switching process of the device, an online extraction technology of key parameters (e.g., voltage rise time) is developed. Finally, an experimental platform for IGBT degradation state estimation is established, and the feasibility of IGBT degradation state estimation based on apparent junction temperature is proved, especially the degradation of bonding-wire and the gate-oxide-layer. The experimental results show that the proposed IGBT degradation state estimation technique based on apparent junction temperature is a reliable online estimation method with non-contact, high accuracy, and comprehensiveness.     

Junction leakage current degradation under the off-statebias-temperature stress: a new reliability assessment method forhigh-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed     

Investigation of fault modes of voltage-fed inverter system forinduction motor drive

The reliability of power electronics systems is of paramount importance in industrial, commercial, aerospace, and military applications. The knowledge about the fault mode behavior of a converter system is extremely important from the standpoint of improved system design, protection, and fault tolerant control. This paper describes a systematic investigation into the various fault modes of a voltage-fed PWM inverter system for induction motor drives. After identifying all the fault modes, a preliminary mathematical analysis has been made for the key fault types, namely, input supply single line to ground fault, rectifier diode short circuit, inverter transistor base drive open, and inverter transistor short-circuit conditions. The predicted fault performances are then substantiated by simulation study. The study has been used to determine stresses in power circuit components and to evaluate satisfactory post-fault steady-state operating regions. The results are equally useful for better protection system design and easy fault diagnosis. They will be used to improve system reliability by using fault tolerant control     

Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage

Tunnel field-effect transistor (TFET) exhibits significant p-i-n forward leakage with the increase in drain-to-source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low-power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p-i-n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished.     

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current I_sub, which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.     

城市电力电缆接头温度无线巡测系统的设计实现

电力电缆中间接头的温度是反映其运行状态的重要参数。通过对接头温度进行测量和监视,可以了解其绝缘老化情况、准确评估其工作状态、及时发现其故障隐患。应用检测技术、计算机技术和通信技术等手段,设计出了一种配置灵活方便的采用无线通信方式的地下专用电网电缆接头温度巡测系统,并介绍了系统的组成及优势。此设备对于避免电缆火灾事故的发生,增强地下专用电网的安全可靠性,提高企业的经济效益有着非常重要的意义。     

Thermal-stability improvement of a sulfur-passivated InGaP/InGaAs/GaAs HFET

The temperature-dependent characteristics of an InGaP/InGaAs/GaAs heterostructure field-effect transistor (HFET), using the (NH/sub 4/)/sub 2/S/sub x/ solution to form the InGaP surface passivation, are studied and demonstrated. The sulfur-passivated device shows significantly improved dc and RF performances over a wide temperature range (300-510 K). With a 1/spl times/100-/spl mu/m/sup 2/ gate-dimension HFET by (NH/sub 4/)/sub 2/S/sub x/ treatment, the considerably improved thermal stability over dc performances including lower temperature variation coefficients on the turn-on voltage (-1.23 mV/K), the gate-drain breakdown voltage (-0.05 mV/K), the gate leakage current (1.04 /spl mu/A/mm/spl middot/K), the threshold voltage (-1.139 mV/K), and the drain-saturation-current operating regimes (-3.11/spl times/10/sup -4//K) are obtained as the temperature is increased from 300 to 510 K. In addition, for RF characteristics, the sulfur-passivated device also shows a low degradation rate on drain-saturation-current operating regimes (-3.29/spl times/10/sup -4//K) as the temperature is increased from 300 to 400 K. These advantages provide the promise for high-speed high-frequency high-temperature electronics applications.     

Reliability of pressure-sensitive adhesive tapes for heat sink attachment in air-cooled electronic assemblies

This study investigates the reliability of commercially available pressure-sensitive adhesive (PSA) tapes used for electronic component-to-heat sink attachment. It is found that creep can affect the PSA reliability. Therefore, creep is experimentally characterized using isothermal, constant load, double lap shear measurements in conditions representative of vertically oriented heat sink applications. PSA joint life predictions are derived from the accelerated creep characteristics using a secondary creep model. The creep resistance of a laminated silicone/aluminum/acrylic PSA tape is found to be significantly lower than that of a single-layer acrylic tape. This suggests that the potential impact of tape creep on joint reliability should be carefully evaluated as a function of tape chemistry/construction and application environment. Furthermore, the sensitivity of PSA creep characteristics to both operating temperature and heat sink weight highlights the need for thermally optimized, least-weight heat sink designs.     

An AC-to-DC Converter with High Quality Input Waveforms

An ac-to-dc converter which draws sinusoidal and inphase current waveforms from the ac power source is described. Harmonic and power factor measurements obtained from a field- effect transistor (FET) converter operating at 45 kHz for a single- phase and a three-phase connection are presented. A stability analysis and design methodology are given.     

面向Si/SiC混合器件逆变器全寿命周期安全工作区的多开关模式主动切换策略

基于硅基绝缘栅双极型晶体管(Si IGBT)和碳化硅金属氧化物半导体场效应管(SiC MOSFET)的Si IGBT/SiC MOSFET混合器件采用多开关模式切换策略可使变换器具备应对复杂工况的能力,然而现有切换策略并未考虑器件疲劳老化对模式切换阈值电流的影响,在混合器件老化进程后期极有可能造成器件热失效,进而严重威胁变换器的可靠运行。基于此,提出了一种面向Si/SiC混合器件逆变器全寿命周期安全工作区的多开关模式主动切换策略。基于器件疲劳老化对逆变器最大安全运行电流的影响规律,设计了考虑老化进程的逆变器安全工作区刻画流程。根据安全工作区刻画结果,提出了适用于混合器件全寿命周期的多开关模式主动切换策略。实验结果表明,该策略能够针对混合器件不同老化程度来动态调整开关模式切换阈值电流,从而在器件全寿命周期内保障逆变器的运行可靠性。     

Supercapacitor Thermal Modeling and Characterization in Transient State for Industrial Applications

A new thermal model, which allows temperature distribution determination inside a supercapacitor cell, is developed. The model is tested for a supercapacitor based on the activated carbon and organic electrolyte technology. In hybrid vehicle applications, supercapacitors are used as energy-storage devices, offering the possibility of providing the peak-power requirement. They are charged and discharged at a high current rate. The problem with this operating mode is the large amount of heat produced in the device which can lead to its destruction. An accurate thermal modeling of the internal temperature is required to design a cooling system for supercapacitor module, meeting the safety and reliability of the power systems. The purpose of this paper is to study the supercapacitor temperature distribution in steady and transient states. A thermal model is developed; it is based on the finite-differential method which allows for the supercapacitor thermal resistance determination. The originality of this paper is in the fact that a thermocouple (type K) was placed inside the supercapacitor from Maxwell Technologies. A test bench is realized. The cases of supercapacitor thermal distribution using natural and forced convection are studied. Simulations and experimental results are reported to validate the proposed model. The results obtained with this model may be used to determine the cooling system required for actual supercapacitor applications.      

Power system operating state forecasting for security analysis applications

A methodology for power system operating state forecasting with applications in the study mode security analysis is described. Additional application areas are advance or dynamic dispatch and measurement replacement. The operating state is represented by the active and reactive nodal injections which are forecast using a four-step procedure: bus active and reactive load forecast, simulation of the economic dispatch and on-line load flow. The multivariate Box and Jenkins approach and the adaptive Kalman filter are used for the active and reactive bus load forecast, respectively. The results of numerical experiments with the proposed methodology indicate a performance with potential for practical applications.     

求解概率动态调度问题的Benders分解算法

概率动态调度能够协调系统运行的经济性与可靠性,相较于传统确定性方法具有先进性.然而,模型规模庞大、求解困难是该类方法所面临的主要问题.提出了一种基于Bentlers分解的新算法对概率动态调度的大型线性规划问题进行求解.该算法针对各种运行状态之间的耦合关系,依据分解协调的思想,采用Benders分解技术将原问题分解,形成...     

MMC器件损耗分布与电容电压纹波综合优化方法

逆变工况下,半桥子模块下部IGBT（简称T2管）损耗占比较大,减小其损耗利于提升设备运行可靠性。同时,抑制电容纹波电压利于减小电容需求及提高功率密度。然而,现有优化控制策略未关注损耗分布优化及电容纹波电压间的矛盾,难以兼顾设备运行可靠性及功率密度。为此,本文提出兼顾减小T2管损耗及抑制电容电压纹波的综合优化方法。首先,通过分析电荷量对器件损耗及电容纹波电压的影响路径,阐述减小T2管的通态损耗与抑制电容电压纹波间的内在矛盾。然后,通过引入罚函数,建立计及T2管损耗及电容电压纹波的综合目标函数。而后,以主动旁路策略为例,通过分析二倍频环流与三次谐波电压注入对T2管损耗和电容电压纹波的影响规律,提出基于二倍频环流及三次谐波电压注入的综合优化方法;最后,在MATLAB/Simulink及PLECS中搭建仿真模型进行验证。仿真结果表明：该综合优化方法兼顾了T2管损耗与电容电压纹波优化,一定程度上增加了设备可靠性与设备的功率密度。