Performance of a packet switch with crossbar architecture

A packet having a crossbar architecture with M inputs and N outputs is considered. Following earlier work, the theoretical capacity of such a switch is found in terms of the throughput of a closed queueing network. A state-dependent server model that approximates the rate at which the switch is transferring packets as a function of the work backlog (the number of packets queued at the switch inputs) is then developed. In this way, the model reflects the fact that such a switch tends to function more efficiently as the work backlog increases. This model yields an accurate method for approximating the entire distribution of the work backlog, as well as mean queue lengths and waiting times     

Performance comparison of switch architectures with shareable parallel memory modules

The class of switches with shareable parallel memory modules include those switches that use parallel memory modules which are physically separate but logically shared. The two main classes of such architectures namely the Shared Multibuffer (SMB) based switch and the Sliding-Window (SW) based packet switch both deploy shareable parallel memory modules, however they differ in the switching scheme used by them to store incoming packets and transfer packets among different switch ports. In this letter, we investigate and compare the performance of switching schemes deployed by these two classes of switching architectures. We compare throughput and packet loss performance of these two switches under conditions of identical traffic type, switch configuration and memory resource deployed.     

PR-banyan: a packet switch with a pseudorandomizer for nonuniformtraffic

Buffered banyan networks are highly vulnerable to nonuniform traffic, due to the path sharing as well as the existence of only a single path per network input-output pair. Improving on an earlier packet distribution network which is a banyan network itself, a single-stage packet-scattering hardware, called the pseudo-randomizer (PR), is proposed. The PR-banyan, the PR followed by a buffered banyan, is analyzed under nonuniform traffic, and is shown to be highly effective under nonuniform traffic. The analytic results are shown to match the simulation results very closely     

The fast packet ring switch: a high-performance efficientarchitecture with multicast capability

An architecture is presented for the packet switching of integrated traffic. It is based on the asynchronous routing of packets of varying size through regularly recurring dedicated time slots provided by a simple slotted-ring system. The architecture implements the distributed buffering and processing of packets, is data driven, and is designed to exploit fully the limited bandwidth of the ring system. Thus, switch modules of reasonable size and throughput are made feasible. The switch modules can be easily interconnected to achieve sufficient throughput for networking of services such as voice, data, image, and videoconferencing. The architecture provides a simple modular switching structure which does not suffer from the topological complexities and bottlenecks of those that use the staged Banyan-type networks for the switching of packets. Quasicircuit-switching can easily be achieved through selected ports with a peak bit-rate bandwidth allocation strategy in the switch control. Multicasting in particular is made simple and efficient in the current architecture. Moreover, it provides for the selective queueing of packets in the transmit ports     

SCOQ: a fast packet switch with shared concentration and outputqueueing

A space-division, nonblocking packet switch with data concentration and output buffering is proposed. The performance of the switch is evaluated with respect to packet loss probability, the first and second moments of the equilibrium queue length and waiting time, throughput, and buffer overflow probability. Numerical results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic. The switch compares favorably with some previously proposed switches in terms of fewer basic building elements used to attain the same degree of output buffering     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

Using a packet switch for circuit-switched traffic: a queueingsystem with periodic input traffic

Consideration is given to the effects of time-multiplexed stream traffic on the performance of a store-and-forward packet switch. Substantially reducing the amount of buffering in the switch results in only a small probability that an existing circuit will be disrupted during the length of its connection. For example, with a circuit-switched frame of length 1000 and 100% loading, reducing the buffer size from 999 packets to 83 results in only a 10^-6 circuit-disruption probability     

MSXmin: a modular multicast ATM packet switch with low delay andhardware complexity

We propose and analyze the architecture for a large-scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(N log² N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log² N) bits. While it is superior to the existing architectures in terms of the hardware complexity and the internal latency, it is comparable to other multicast switches in terms of the header overhead and translation table complexity. MSXmin is output buffered and based on the group knockout principle. Moreover, MSXmin is a dual-bit-controlled tree-based switch     

A decentralized indirect adaptive control for a class oftwo-time-scale nonlinear systems with application to flexible-jointmanipulators

In this paper, the problem of an indirect adaptive decentralized control for a class of two-time scale interconnected systems is considered. The concept of an integral manifold is first utilized to construct the dynamics of corrected slow subsystems. Fast subsystems are also constructed to represent the dynamics of the fast modes. A composite control scheme based on full state feedback is then developed to guarantee stability and robustness of the closed-loop system. The controller is designed by taking into account the effects of unmodeled dynamics, identification errors, and parameter variations. Stability analysis of the resulting closed-loop full-order system subject to the composite controller is presented. To demonstrate the application of the proposed algorithm, an example of a two-link flexible-joint manipulator is considered. Simulation results are provided to validate the applicability of the proposed control scheme     

Sliding mode control with closed-loop filtering architecture for a class of nonlinear systems

It is well known by equivalent control theory, that in the sliding mode a low-pass filter, working as an average operator, can capture the desired control fairly well from the switching control signals. However, directly adding the filtered signals in parallel with the switching control does not warrant any improvement in the control system performance. In this work, we make clear the underlying reason why the sliding mode control (SMC) system does not function properly with such a simple closed-loop filtering structure. The correct way of incorporating the closed-loop filtering into SMC requires a second low-pass filter, which works concurrently with the first low pass filter to scale down the gain of the switching control. The SMC system with the new closed-loop filtering is able to realize the acquisition of equivalent control or estimate the disturbance, effectively reduce the switching gain to the minimum level, and as a result to eliminate chattering. Complementary to existing SMC, the proposed control system can easily incorporate feed-forward control into the closed-loop for bounded system perturbations. In addition, the frequency-domain knowledge can be easily used to construct the two filters.     

Input and output queueing ATM switch architecture with spatial and temporal slot reservation control

A viable ATM switch architecture exploiting both input and output queueing on a space division switch is proposed. This architecture features both input and output ports that are divided into several groups, and an efficient contention resolution algorithm is developed. The performance study indicates that a group size of eight is sufficient to achieve 90% efficiency.<>     

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns     

Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets

Traditionally, conflict resolution in an input- buffered switch is solved by finding a matching between inputs and outputs per time slot, which incurs unscalable computation and communication overheads. The main objective of this paper is to propose a scalable solution, called the mailbox switch, that solves the out-of-sequence problem in the two-stage switch architecture. The key idea of the mailbox switch is to use a set of symmetric connection patterns to create a feedback path for packet departure times. With the information of packet departure times, the mailbox switch can schedule packets so that they depart in the order of their arrivals. Despite the simplicity of the mailbox switch, we show via both the theoretical models and simulations that the throughput of the mailbox switch can be as high as 75%. With limited resequencing delay, a modified version of the mailbox switch achieves 95% throughput. We also propose a recursive way to construct the switch fabrics for the set of symmetric connection patterns. If the number of inputs, N, is a power of 2, we show that the switch fabric for the mailbox switch can be built with y log2 N 2 x 2 switches.     

CDMA无线分组网中新MAC协议的研究

该文在语音与数据混合的CDMA无线网络中提出了一种新的媒质访问控制（MAC）协议MSADQ（Minislot signaling Access based on double Queue)。该协议基于分布队列及冲突解决算法，通过对PN码字的有序管理，从而大大减少随机竞争的冲突，降低多址接入干扰，节省PN码码资源。提出了码字分配算法和队列管理算法，对语音和数据业务进行QoS保证。对协议的性能进行了仿真，并与其他两种预约协议进行了比较，结果表明，MSADQ／CDMA协议使用较少的PN码字却仍然有很好的性能。     

The performance analysis and implementation of an input accessscheme in a high-speed packet switch

The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input port maintains a separate queue for each of the outputs, thus n ² input queues in an (n×n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. We derive lower and upper bounds for the throughput which show close to optimal performance. The bounds are very tight and approach to unity for switch sizes on the order of a hundred under any traffic load, which is a significant result by itself. Then the mean packet delay is derived and its variance is bounded. A neural network implementation of this input access scheme is given. The energy function of the network, its optimized parameters and the connection matrix are determined. Simulation results of the neural network fall between the theoretical throughput bounds     

接入交换机体系结构及其性能的研究

本文首先综述了接入交换机结构的发展,详细介绍了基于ASIC的接入交换机结构和可伸缩的接入交换机结构,给出了基于可伸缩结构的原型样机软硬件结构设计,对原型样机采用不同处理器的存储转发能力和综合接入性能进行了测试和分析,结果表明采用上述体系结构可以设计出高性能价格比的接入交换机。     

Design of a decentralized modular architecture for flexible and extensible production systems

In the European manufacturing industry, production batches are decreasing, resulting in an increase in required changeovers. Companies are pushed to respond quickly and cost-efficient to changing markets. One way for Small and Medium sized Enterprises (SMEs) to become more agile, is to incorporate industrial robots in their production processes; larger enterprises already use this versatile piece of equipment for large batch sizes. To do so, a new perspective and approach is required, tailored to dynamic manufacturing systems in which production systems and components can be easily reconfigured, altered, swapped or replaced. A modular system architecture was developed within project SInBot upon which challenges in dynamic cooperation between robots and humans were projected. The developed system uses decentralized control and distributed intelligence, linked through an extensible, flexible, and fault-tolerant communication architecture. The rapidly growing complexity of traditional systems is compared to its decentralized counterpart to illustrate some of the many advantages of this new system architecture. A manufacturing scenario analogue is discussed and the approach to verify the performance of inner-system components, as well as the benefits of this approach. Key challenges that are encountered in implementing the cooperation into the current industrial environments are identified and projected upon the verification system.     

OPSnet: design and demonstration of an asynchronous high-speed optical packet switch

This paper presents the results of the optical packet switched network (OPSnet) project, which investigated the design of an asynchronous optical packet switch suitable for the core of an optical transport network (OTN). The requirements for the switch were to control and route variable-length packets transmitted at bit rates beyond 100 Gbit/s. The subsystems and techniques used are analyzed and presented. Fast header encoding and passive decoding is based on the differential phase-shift keying (DPSK) method. The dual-pump four-wave mixing (d-p FWM) wavelength-conversion technique, in combination with an arrayed waveguide grating (AWG), is utilized for packet switching. An advanced and fully controllable mechanism for the packet-switch control is presented, which is implemented on field programmable gate array (FPGA) technology. The control wavelength is generated using a tunable laser, the actual wavelength and new header values are provided utilizing fast header recognition and look-up tables. The integration of the subsystems is discussed, and the results of a four-output port asynchronous packet-switch demonstrator operating at 40 Gbit/s are presented. Finally, the switch limitations are examined and design issues are discussed.     

The augmented data vortex switch fabric: An all-optical packet switched interconnection network with enhanced fault tolerance

Optical Multistage Interconnection Networks (OMINs) are capable of transmitting terabits of bandwidth per second, and they have been considered as possible solutions to the electronic communications bottleneck in interconnection networks. A novel architecture, the Data Vortex (DV) switch, has been proposed by Yang et al., as a scalable, ultra low latency, ultra high capacity, high throughput, low cross-talk and low BER, all-optical packet switching fabric that is a suitable candidate for use as an OMIN. For any interconnection network, its fault tolerance and reliability are crucial issues, which have lacked attention up to now in the case for a DV switch. In this paper we, therefore, present results of fault tolerance and reliability analysis of the primary DV switch, and propose (1) a new Augmented Data Vortex (ADV) switch fabric, to improve the fault tolerance of the primary DV switch. (2) The labelling and a numbering scheme, with detailed interconnections of nodes for the ADV switch is given. (3) A new self-routing procedure and a priority scheme for distributed control signalling in the ADV switch have been given. (4) For the first time, conversion of the 3-dimensional switch to an equivalent chained-MIN model, has been given, which is more suitable for later analysis of fault tolerance. (5) A multiplexing scheme at input ports and output ports which further enhances the fault tolerance of the ADV switch has been given. (6) Computation has been done of the reliability and fault tolerance of the new architecture via an analytical model. (7) Finally, comparison of the ADV switch architecture with the primary architecture (DV) in view of fault tolerance and reliability has been given, and hardware complexity and cost effectiveness have been studied.     

一种新型开关表的PWM整流器直接功率控制

为了提高三相电压电压型PWM整流器的性能,改善传统开关表的直接功率控制时开关损耗大且不固定,以及有功功率和无功功率控制解耦能力不足的问题,文中通过对PWM整流器和瞬时功率理论研究的基础上,提出一种基于三电平比较器的新的开关表直接功率的方法,并通过设置扇形边界死区的控制策略细分开关表,这种新开关表通过消除两个扇区中间区域的错误控制,能较好的降低主电路开关频率,增加功率控制性能,使交流侧电流输入谐波率更小,提高整流器的功率因数。在MATLAB/Simulink环境下,对改进前后直接功率控制的稳态性能进行比较,验证了该设计方法的可行性,具有应用参考价值。