Comments on the optimum CMOS tapered buffer problem

Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations     

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.     

High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.     

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

Design of CMOS tapered buffer for minimum power-delay product

The tapered buffer is analyzed from the viewpoint of power dissipation. Both uniform and nonuniform tapered buffers are considered. It is found that there is an optimum value of tapering factor for a minimum power-delay product. In case of uniform tapering, we can obtain an analytical solution of the optimum tapering factor for a minimum power-delay product, which is about 1.5~2 times larger than that for a minimum propagation delay. It is also found that there exists a nonuniform tapering factor which gives a global optimum condition for a minimum power-delay product, which, however, results in a larger short-circuit current. Compared with a uniform buffer, a nonuniform tapered buffer shows about 8% improvement in dynamic switching energy, and 3~5% improvement in total switching energy. We confirm this by simulating tapered buffers with SPICE     

使用变比例到定比例的方法优化CMOS串联缓冲器链的设计

本文提出了一种新的变比例到定比例(variable to fixed,VF)的CMOS串联缓冲器链的设计方法.这种VF的设计方法考虑了一个由倒相器组成的缓冲器链的初始输入波形斜率对其每一级时延的影响.同时,计算了倒相器的前馈电容对时延的影响.并着重研究了以上因素所导致的缓冲器链前几级的特殊性质,并据此提出了一个考虑初始波形的全局的倒相器链的优化方法.对每个倒相器的输出响应,我们提出了一组解析表达式.理论推导和SPICE的模拟证明,我们的VF设计方法是一个针对时延的最优解,面积相应较小.实验数据显示:与传统的常比例方法相比,可以节省6~10%的时延和30~70%的面积.     

Modeling the influence of the transistor gain ratio and theinput-to-output coupling capacitance on the CMOS inverter delay

An improved model for the ramp response of a CMOS inverter has been derived where the influences of the short-circuit current and the input-to-output coupling capacitance are considered. These effects modify the ideal linear relationship between the inverter propagation delay and the input ramp rise/fall time by adding a term proportional to the charge supplied by the short-circuiting transistor. This term is shown to contain first- and second-order contributions of the input ramp rise/fall time where the second-order contribution effectively models the propagation delay roll-off for slow input ramps. Both the first and the second-order effects are found to be affected by the P-to-N-channel gain ratio. The model shows excellent agreement with SPICE level 3 simulations; even when the short-circuiting transistor has a driving capability twice that of the charging/discharging transistor the error in the propagation delay is only about 2% for a slow input ramp (input-to-output slope-ratio at V_DD/2 equal to 1:2)     

Area-efficient layout design for CMOS output transistors

A novel layout design to effectively reduce the layout area of the thin-oxide NMOS and PMOS devices in CMOS output buffers with ESD consideration is proposed. With respect to the traditional finger-type layout, the large-dimension output NMOS and PMOS devices are realized by multiple octagonal cells. Without using extra ESD-optimization process, the output NMOS and PMOS devices in this octagon-type layout can provide higher driving/sinking current and better ESD robustness within a smaller layout area. The drain-to-bulk parasitic capacitance at the output node is also reduced by this octagon-type layout. Experimental results in a 0.6-μm CMOS process have shown that the output driving (sinking) current of CMOS output buffers in per unit layout area is increased 47.7% (34.3%) by this octagon-type layout. The HBM (MM) ESD robustness of this octagon-type output buffer in per unit layout area is also increased 41.5% (84.6%), as comparing to the traditional finger-type output buffer. This octagon-type layout design makes a substantial contribution to the submicron or deep-submicron CMOS IC's in high-density and high-speed applications     

An analytical charge-based compact delay model for submicrometer CMOS inverters

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-/spl mu/m and a 0.35-/spl mu/m process technologies show significant improvements over previous models.     

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT², the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with V_DD = 1 V, minimum size gate capacitance, C_g = 1.5 fF, and minimum size output capacitance, C_o = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.     

Channel width tapering of serially connected MOSFET's with emphasison power dissipation

Transistor channel width tapering in serial MOSFET chains is shown in this paper to simultaneously decrease propagation delay, power dissipation, and physical area of VLSI circuits. Tapering is the process of decreasing the size of each MOSFET transistor width along a serial chain such that the largest transistor is connected to the power supply and the smallest is connected to the output node. A detailed explanation of the effects of tapering on the output waveform is presented with specific emphasis on the power dissipation of tapered chains. It is demonstrated that in many cases tapering decreases delay and changes the shape of the output waveform such that the time during which a load inverter is conducting short-circuit current is reduced. This decrease in short-circuit current also occurs in many cases where tapering may not offer a speed advantage. In addition, dynamic CV²f power dissipation of the serial chain is reduced. In those circuits where tapering does not decrease propagation delay, tapering permits a designer to tradeoff speed for a reduction in both short-circuit and dynamic power dissipation, a tradeoff not normally available with untapered chains. Thus the total power consumed by a serial chain of MOSFET's, as well as its propagation delay and area, can be reduced by channel width tapering. A design system for determining when tapering is appropriate, selecting the amount of tapering, and synthesizing the physical layout is presented. Physical layout issues unique to tapering are discussed, and fabricated test structures are described     

A comprehensive delay macro modeling for submicrometer CMOS logics

The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-μm foundry specified card model) used as a reference     

Semi-static threshold-triggered delay elements for low power operation

Delay elements are widely used in mixed signal integrated circuits in order to meet design-specific timing requirements. Generally delays are generated by lengthening the transition times of the input signal which is subsequently restored. Slow transition times however, results in prolonged short-circuit current duration at the signal restoration stage, not only increasing the overall power consumption of the system but also limiting the usable output delay range. This paper presents a novel CMOS semi-static threshold-triggered delay element architecture that minimizes the short-circuit current over a wide output delay range. The architecture can also incorporate conventional delay elements to improve their performance. The presented delay element is fabricated in a commercial 0.35 μm CMOS technology and the measurement results show significant improvements in output delay range and average power consumption over other conventional delay elements.     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed     

Design of tapered buffers with local interconnect capacitance

This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C³RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore, the propagation delay of each buffer stage also remains constant. Reductions in power dissipation of up to 22% and reductions in active area of up to 46%, coupled with reductions in propagation delay of up to 2%, as compared with tapered buffers which neglect local interconnect capacitance, are exhibited for an example buffer system     

A low-power high-speed class-AB buffer amplifier forflat-panel-display application

A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 μm CMOS technology     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.