Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

A very high precision 500-nA CMOS floating-gate analog voltage reference

A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.     

基于65 nm CMOS工艺的2阶温度补偿全CMOS电压基准源

采用65 nm CMOS工艺,设计了一种基于MOS亚阈区特性的全CMOS结构电压基准源.首先利用工作在亚阈值区NMOS管的栅源电压间的差值得到具有特定2阶温度特性的CTAT电压,该CTAT电压的2阶温度特性与PTAT电压2阶温度特性的弯曲方向相反.再通过电流镜技术实现CTAT电压和PTAT电压求和,最终得到具有2阶温度...     

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V/sub th/ deep-submicrometer 0.12-/spl mu/m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25/spl deg/C-220/spl deg/C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.     

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20/spl deg/C to 110/spl deg/C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V//spl deg/C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV//spl deg/C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V//spl deg/C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A two-terminal IC temperature transducer

A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl deg/C has been designed, fabricated, and tested. The two-terminal device, which is fabricated using laser trimmed thin-film-on-silicon technology, is a calibrated temperature dependent current source with an average output impedence of 10 M/spl Omega/ over the 3.5-V to 30-V range of input voltage. Overall absolute accuracies of /spl plusmn/0.5/spl deg/C from -75/spl deg/C to +150/spl deg/C have been achieved on a scale of 1 /spl mu/A/K under optimum operating conditions.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的栽流子迁移率和亚闽值斜率的温度系数。基于SMIC0．13μm的CMOS工艺的仿真结果表明,在-5-90℃的范围内。输出电压的温度系数为5ppm／℃。在室温时,整个电路能在低到0．9V的电源电压下工作并消耗0．68μW的功耗。     

High-density CMOS ROM arrays

A single transistor cell and a precharge signal are used to reduce the memory cell area in bulk CMOS ROM arrays to 1.12 mil/SUP 2//bit. Use of SOS/CMOS technology further reduces the memory cell area to 0.38 mil/SUP 2//bit and makes possible CMOS ROMs of up to 32768 bits. Operation of both the array and the decoders is controlled by a precharge signal which is generated internally in a way which is transparent to the user. The CMOS ROMs thus produced are competitive with NMOS ROMs in both density and speed, yet retain all of the advantages of static CMOS circuits such as 1-/spl mu/W power dissipation, full 2.8-15 V voltage operating range, and full -55/spl deg/C-125/spl deg/C temperature range.     

高电源抑制比的CMOS亚阈值多输出电压基准

基于工作在亚阈值区的MOS器件,运用CMOS电流模基准对CATA和PTAT电流求和的思想．提出一种具有低温漂系数、高电源抑制比（PSRR）的CMOS电压基准源,该电路可同时提供多个输出基准电压,且输出电压可调。该基准源基于CSMC0．5μm标准CMOS工艺,充分利用预调节电路并改进电流模基准核心电路。使整个电路的电源抑制比在低频时达到122dB,温度系数（TC）在0-100℃的温度范围内约7ppm／℃。     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.