Loosely coupled multi-bit flip-flop allocation for power reduction

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

新型低噪声电流型CMOS边沿触发器设计

提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在有效时钟沿后产生的窄脉冲使锁存器瞬时导通完成一次取样求值。与主从型触发器相比,单闩锁结构的触发器具有结构简单、直流功耗低的特点。采用0.25μm CM O S工艺参数的HSP ICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CM O S电路。     

Test response compaction method with improved detection and diagnostic abilities

This paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

Design of high-speed bipolar flip-flops for reduced clock loading

A new topology for flip-flops is presented. A current amplifier is incorporated into a standard, current mode logic, D-type flip-flop. The gain cell effectively buffers the clock without requiring additional current. Level shifting emitter followers from the clock are reduced in size and current. The frequency response of the gain cell selectively applies a keep-alive current to the circuit at high frequency without distorting low frequency outputs. The flip-flop is configured as a static frequency divider and compared to a standard flip-flop in a bipolar SiGe process. The new circuit is faster and requires less clock power at high frequency, making it suitable for large-scale integration.     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.     

Partial scan flip-flop selection by use of empirical testability

Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.     

Conditional-capture flip-flop for statistical power reduction

This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-μm CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop     

新型半静态低功耗D触发器设计

本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。PSPICE模拟表明，新设计逻辑功能正确。与以往一些设计相比，新设计在功耗和速度上获得显著改进。     

Low power double edge-triggered flip-flop using one latch

A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops     

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

Product-term-based synthesizable embedded programmable logic cores

As integrated circuits become increasingly complex, the ability to make post-fabrication changes will become more important and attractive. This capability can be realized by using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" macro layouts. Previous work has suggested an alternative approach: vendors supply a synthesizable version of their programmable logic core and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased delay, area, and power, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or system-on-chip (SoC). When implementing a small amount of logic, this ease of use may be more important than the increased overhead. This paper presents a new family of architectures for these "synthesizable" cores; unlike previous architectures, which were based on lookup-tables (LUTs), the new family of architectures is based on a collection of product-term arrays. Compared to LUT-based architectures, the new architectures result in density improvements of 35% and speed improvements of 72% on standard benchmark circuits. The improvement is due to the inherent efficiency of product-term-based designs for small logic circuits. In addition, we describe novel ways of enhancing synthesizable architectures to support sequential logic. We show that directly embedding flip-flops as is done in stand-alone programmable cores will not suffice. Consequently, we present two novel architectures employing our solution and optimize and compare them. Finally, we describe a proof-of-concept layout employing one of our proposed architectures.     

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology     

New dynamic flip-flops for high-speed dual-modulus prescaler

A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D flip-flops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. Also it is suitable for realizing high-speed synchronous counters. A divide-by-128/129 and 64/65 dual-modulus prescaler using the proposed flip-flops is measured in 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.8 GHz     

能量回收技术在D触发器上的应用

将能量回收技术应用于灵敏放大器型D触发器(SAERD),该电路采用单相正弦时钟,用来回收时钟端的能量,对于触发器的内部节点和存储单元仍采用恒定电源。在时钟频率为100～300MHz时,时钟端的功耗较输入方波时平均节省约80%。在SMIC0.13μm工艺下将SAERD应用于一款函数发生器,并与传统主从型D触发器(MSD)实现的电路进行功耗比较。仿真结果显示,时钟频率为200MHz时,功耗节省高达17.1%。     

Synchronous derived clock and synthesis of low power sequential circuits

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.     

A novel clocking technique for VLSI circuit testability

Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these requirements for certain designs with static flip-flops that are controlled by two independent signals (master clock and slave clock). This is possible because, in normal circuit operation, the master and slave clocks are never simultaneously active. The new clocking structure uses the `all clocks active' condition to specify the scan mode. Implementation of the concept is discussed in detail for two-clock circuits. Single-clock circuits can be modified to use this scheme, and the results for this class of design are also presented.     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity