金属线宽及线间距渐变的射频螺旋电感

为减少射频螺旋电感的金属导体损耗,提出了一种电感金属线宽及金属间距从外到内逐渐变小的新颖结构.与传统的固定金属线宽和间距的电感相比,该渐变结构电感涡流效应的影响较小,金属导体损耗减小,从而降低其串联电阻,品质因子Q值提高.实验结果确证了所提方法的正确性.对一个高阻硅衬底上6nH电感,优化设计的渐变结构电感Q值在2.46GHz处可达到14.25,比版图面积相同、固定线宽及间距的传统电感高11.3%.因此,在无线通信系统的射频前端,采用这种电感与射频集成电路结合,能获得更好的射频电路性能.     

Improving the quality factor of an RF spiral inductor with non-uniform metal width and non-uniform coil spacing

An improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor(Q factor).For this inductor layout,from outer coil to inner coil,the metal width is reduced by an arithmetic-progression step,while the metal spacing is increased by a geometric-progression step. An improved layout with variable width and changed spacing is of benefit to the Q factor of RF spiral inductor improvement(approximately 42.86%),mainly due to the suppression of eddy-current loss by weakening the current crowding effect in the center of the spiral inductor.In order to increase the Q factor further,for the novel inductor, a patterned ground shield is used with optimized layout together.The results indicate that,in the range of 0.5 to 16 GHz,the Q factor of the novel inductor is at an optimum,which improves by 67%more than conventional inductors with uniform geometry dimensions(equal width and equal spacing),is enhanced by nearly 23%more than a PGS inductor with uniform geometry dimensions,and improves by almost 20%more than an inductor with an improved layout.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency     

Analytical formula for inductance of metal of various widths in spiral inductors

This paper presents an analytical formula for the inductance of an inductor with the layout of variable metal width, based on the quasistatic approximation. Experimental results indicate that the analytical formula is feasible. A layout with metal whose width increases monotonously from the inner turn has a higher Q value than other configurations of the metal with the same inductance. This information will be of help in designing high-performance inductors for RF integrated circuit applications.     

金属线宽与间距渐变的片上螺旋电感设计规则研究

在分析片上螺旋电感的磁场分布及射频损耗机制的基础上,研究了电感的金属线宽及线圈间距的变化对电感性能的影响,在大量数值分析基础上提出了金属线宽与间距之和不变,而金属线宽与间距之比从外圈到内圈逐渐减小的渐变型片上螺旋电感,并得到了实验验证,多组样品的测试结果与数值分析结果相吻合,以2.4 GHz频段处为例,在高阻硅衬底上制备的5 nH渐变结构电感的品质因子Q为11,比具有相同外径和电感值的固定金属线宽及间距的传统电感高19.6%.     

RF集成电感的设计与寄生效应分析

分析了体硅 CMOS RF集成电路中电感的寄生效应 ,以及版图参数对电感品质因数 Q的影响 ,并通过Matlab程序模拟了在衬底电阻、金属条厚度、氧化层厚度改变时电感品质因数的变化 ,分析了不同应用频率时版图参数在寄生效应中所起的作用 ,得出了几条实用的设计原则并进行了实验验证 ,实验结果与模拟值符合得很好 ,表明此模拟方法与所得结论均可有效地用于指导射频 (RF)集成电路中集成电感的设计     

非均匀金属线宽和线间距射频螺旋电感品质因子的改善

为了提高品质因子Q,本文提出了一种非均匀金属条宽和非均匀条间距的改进电感结构。从外圈到里圈,改进的电感金属线宽按等差数列逐渐减小,金属间距按等比数列增加。因为该渐变结构有效减弱了线圈中心电流拥挤导致的涡流效应,所以改进结构电感的Q因子大幅度提高（幅值高达42.86%）。为了进一步增大Q因子,新型电感同时采用图形化接地保护结构（PGS）与渐变结构。结果显示,在0.5GHz到16GHz的射频频段内,结合两种技术的新型电感的品质因子Q最优,与固定金属线宽和间距的传统电感相比,Q提高了67%;与仅采纳PGS结构的电感相比,Q提高了23%;与仅采用渐变金属结构的电感相比,Q提高了20%。     

A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on-chip integrated inductor, a concise method to increase the Q factor has been ob tained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5 % compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.     

A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.     

Coupling Effect of On-Chip Inductor With Variable Metal Width

This study proposes a proper layout of on-chip inductors to diminish the coupling effect in silicon-based technology. Keeping self inductance constant, the mutual inductance is measured to characterize coupling effect in three test keys. A layout with variable metal width of inductor is found to alleviate mutual inductance. Experiment results demonstrate the mutual inductance decreases 33.5% compared with standard layout. This information will be helpful in implementation of more than one inductor into radio frequency integrated circuits (RFICs).     

Equivalent Circuit Analysis of an RF Integrated Inductor with Ferrite Thin-Film

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

This paper presents a rigorous investigation of high-frequency effects in carbon nanotube (CNT) interconnects and their implications for the design and performance analysis of high-quality on-chip inductors. A frequency-dependent impedance extraction method is developed for both single-walled CNT (SWCNT) and multiwalled CNT (MWCNT) bundle interconnects. The method is subsequently verified by comparing the results with those derived directly from the Maxwell's equations. Our analysis reveals for the first time that skin effect in CNT (particularly MWCNT) bundles is significantly reduced compared to that in conventional metal conductors, which makes them very attractive and promising material for high-frequency applications, including high-quality (Q) factor on-chip inductor design in high-performance RF/mixed-signal circuits. It is shown that such unique high-frequency properties of CNTs essentially arise due to their large momentum relaxation time (leading to their large kinetic inductance), which causes the skin depths to saturate with frequency and thereby limits resistance increase at high frequencies in a bundle structure. It is subsequently shown that CNT-based planar spiral inductors can achieve more than three times higher Q factor than their Cu-based counterparts without using any magnetic materials or Q factor enhancement techniques.     

RF平面螺旋微电感计算机模拟研究

应用Greenhouse法对RF平面螺旋微电感进行了计算机模拟,探明了微电感品质因数Q值在高频域内的变化规律,得出了微电感金属层厚度、线宽、线间距及线圈数与RF平面螺旋微电感Q值的对应关系。研究发现,RF平面螺旋微电感的Q值在高频域内随频率增加而呈现先升高后下降的趋势,Q值存在峰值;微电感Q值在某一频率范围内随微电感金属层厚度、线宽的增加而增大;随线间距的增加,微电感的低频性能下降而高频(>1GHz)性能升高;当微电感直径一定时,随线圈数的增加,Q值有下降的趋势。     

Investigation on the layout parameters of on-chip inductor

A comprehensive discussion on the layout parameters of spiral inductor is addressed in this paper. By keeping the identical DC resistance, the variations of metal width, coil number, and metal spacing influence the RF resistance are investigated completely. Then the mechanism of induced eddy current is described to explain the influence in the design of layout parameters. Finally, the experimental result of special layout (i.e. taper inductor) is demonstrated the improved Q characteristics.     

铁氧体磁膜RF集成微电感等效电路分析

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

Method of creating local semi-insulating regions on silicon wafersfor device isolation and realization of high-Q inductors

Penetrating proton beams from a compact ion cyclotron (diameter: 1.5 m, height: 2 m) were employed to create local semi-insulating regions within silicon substrates to facilitate device isolation in mixed-mode (analog-digital) integrated circuits (IC's) and realization of RF IC's with high-Q inductors. Experiments revealed that resistivity values of I MΩ-cm could be reached by practical proton fluences on silicon wafers of original resistivity of more than about 1 Ω-cm. Significant improvement was evidenced on Q values of irradiated inductors. Effect of reduced inductor metal conductivity from bombardment was over-shadowed by the more enhanced Q behavior, if the proton fluence is sufficiently large     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f _res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65–95% over conventional planar symmetric inductors and 71–94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC’s will be reduced significantly.     

The detailed analysis of high Q CMOS-compatible microwave spiralinductors in silicon technology

We present the extensive experimental results and their detailed analysis showing the important effects of layout parameters on the frequency responses of quality factor (Q) of rectangular spiral inductors, which are fabricated on a silicon substrate by using conventional silicon CMOS technology, in order to determine the desirable values of layout parameters for designing the high Q inductors used in RF IC's applications. Analysis of the inductors on Si substrates with three kinds of resistivities has been performed by tailoring the geometric layout and varying the metal thickness. Using these results, the substrate effects on RF performance of inductors are also investigated by observing the frequency responses of Q with varying the substrate resistivity in detail     

宽带硅衬底RF片上螺旋电感物理模型

针对高损耗硅衬底,源自部分元等效电路方法考虑了趋肤效应和邻近效应对螺旋电感中串联电感L_s、串联电阻R_s频率特性的制约,并基于全耦合变压器模型计入了复杂的衬底涡流损耗,从而建立了一种新的片上螺旋电感物理模型.通过与全波分析方法对比,验证了在20GHz范围内由该模型导出的等效电感L_eff、等效电阻R_eff和Q值误差仅在7%以内.该模型可望用于硅基射频集成电路中电感进一步的理论探讨和优化设计.