A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A front-end processor for modems

A front-end processor constructed of an oversampling delta-sigma ADC/DAC (analog-to-digital converter/digital-to-analog converter) and a digital signal processor is described. The chip can handle a maximum of eight different processing modes for modem applications including the echo canceling scheme. The chip incorporates a voltage reference circuit, digital PLL (phase-locked loop), and a unique second interpolation circuit to realize both conventional QAM (quadrature amplitude modulation) demodulation and echo cancel-type demodulation. The chip is fabricated in a 1.5-μm double-poly double-metal CMOS process. The chip size is 9.2 mm×7.2 mm, and the typical power consumption is 150 mW with a single +5.0-V power supply     

A power and area efficient CMOS clock/data recovery circuit forhigh-speed serial interfaces

A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm² for the digital PLL and 0.44 mm² for the analog PLL. It can handle an input data rate up to 280 Mb/s     

A CMOS 5-V analog front end for 9600-bit/s facsimile modems

A CMOS 9600-b/s facsimile-modem analog front end was designed with the consideration that it be capable of being fabricated on the same chip with digital signal processing circuits. To achieve the dynamic range required in the high-speed QAM (quadrature amplitude modulation) modem environment with a single 5-V power supply, a fully differential architecture is used. The die area is 23 kmil/SUP 2/ and the power consumption is only 35 mW. The experimental results show that 76-dB dynamic range is achieved from the fully differential bandpass filter. The zero crossing detector in the MF-1 detection block can normally operate with -50-dBm input signal.     

A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.     

A single-chip 5-V 2400-b/s modem

A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The receiver is performed almost entirely in the analog domain. The IC also supports a number of lower-speed (⩽1200 b/s) split-band modem standards. The chip occupies 68.8 mm² and dissipates 120 mW while operating off a single 5-V supply. System and circuit aspects of the design are discussed, and the measured performance of the IC is summarized     

DIFFS: A Low Power,Multi-Mode,Multi-Standard Flexible Digital Front-End for Sensing in Future Cognitive Radios

Cognitive Radios provide communication devices with the flexibility to adjust to varying network and channel conditions. For this to be fully realizable spectrum sensing and signal reception have to happen simultaneously and have to require as little power as necessary to function in handheld devices. This work argues for the need of flexible digital-front ends as indispensable building block, able to perform control operations over the analog front-end and to perform sensing and synchronization procedures without the need of power consuming baseband processors. A low power, reconfigurable digital front-end that supports concurrent synchronization and sensing of high-throughput wireless standards is presented. Multiple operating modes, useful for various communication standards, such as LTE, WLAN and DVB-T are introduced and analyzed. The digital front-end has been implemented in 65 nm CMOS technology resulting in a chip area of 6.4 mm2. Fine grain clock gating allows synchronization at 4 mW and sensing at 7 mW power consumption. Experiments in combination with a reconfigurable analog front-end show that a 1.7 GHz wide frequency band can be scanned based on energy detection in an exceptionally low time window of 10 ms while consuming 13 mW power and that coarse energy detection can speed-up the sensing process. Furthermore, advanced feature detection for DVB-T and LTE signals is implemented and measured. Low power sensing of DVB-T signals shows that a target false alarm rate of 10 % and a detection probability of 90 % at an input power level of?106 dBm while consuming 7 mW power are possible. Synchronization-aided FFT-based LTE sensing with leakage cancellation was experimentally validated for various bandwidths showing a power consumption of maximum 20 mW.     

A 3-V 0.5-μm CMOS A/D audio processor for a microphone array

A 0.5-μm 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm², and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications     

A Multimode Transmitter in 0.13 μm CMOS Using Direct-Digital RF Modulator

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm².     

Chip for linearisation of RF power amplifiers using digitalpredistortion

A digital VLSI chip is presented that implements the most critical part of a predistortion system for linearisation of RF power amplifiers. Measurements have shown that the chip provides seven times higher modulation bandwidth (208 kHz) at 10% power (100 mW) compared with a standard digital signal processor     

Fabrication, RE performance, and yield of a combined limitingamplifier and dual-modulus prescalar GaAs IC chip

Production technology details, RF performance, and yield results for an ECL-compatible, L-band, limiting dual-modulus (÷10/11) prescalar are presented. Monolithic integration of analog and digital circuit functions is achieved using refractory self-aligned-gate FET technology. When tested with -22-dBm input signal power, one lot of six wafers had a total RF chip yield of 19% with a best-wafer yield of 43%. The average operating frequency was 1.45 GHz (SD=51 MHz) with an average power dissipation of 696 mW (SD=23 mW)     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

Monolithic optical position encoder with on-chip photodiodes

A system that combines light sensors and analog and digital parts on the same CMOS chip has been fabricated. The optical and electrical properties of various photodiodes, which are fully compatible with a standard CMOS technology, are discussed. The current comparators use CMOS-compatible lateral bipolar transistors. The optical encoder also comprises a signal processor for code conversion, a serial or parallel output, and a self-test function. A 14-channel circuit which senses light signals at 880 nm with a power of 0.3-3 mW/cm² has been fabricated. Response time is shorter than 1 μs at all illumination levels. This circuit operates in the temperature range -55 to +125°C. Its current consumption is 8 mA at 5 V     

A DSP-based hearing instrument IC

This paper presents a digital signal processing IC, including AD/DA converters, for one-chip hearing instruments. An on-chip infrared remote control receiver is used to load a program Into the digital signal processor (DSP). The complete IC consumes 2 mW from a single cell battery and operates with supply voltages down to 0.9 V. The oversampling A/D and D/A converters show a dynamic range of 77 and 93 dBA, respectively. Only a few external capacitors are needed. The chip area is 35 mm² in a low-threshold 0.8-μm CMOS process     

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture

An analog computing-based systolic architecture which employs multiple neuroprocessors for high-speed early vision processing is presented. For a two-dimensional image, parallel processing is performed in the row direction and pipelined processing is performed in the column direction. The mixed analog/digital design approach is suitable for implementation of electronic neural systems. Local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Inter-processor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to achieve direct scalability in neural network size. For demonstration purposes, a compact and efficient VLSI neural chip that includes multiple neuroprocessors for high-speed digital image restoration is designed. Measured results of the programmable synapse, and statistical distribution of measured synapse conductances are presented. Based on these results, system-level analyses at 8-bit resolution are conducted. A 8.0×6.0-mm ² chip from a 1.2-µm CMOS technology can accommodate 5 neuroprocessors and the speed-up factor over the Sun-4/75 SPARC workstation is around 450. This chip achieves 18 Giga connections per second.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by TRW Inc., Samsung Electronics Co., Ltd., and NKK Corp.     

A low-power analog motion estimation processor for digital video coding

Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.