3D集成晶圆键合装备现状及研究进展

硅基异构集成和三维集成可满足电子系统小型化高密度集成、多功能高性能集成、小体积低成本集成的需求,有望成为下一代集成电路的使能技术,是集成电路领域当前和今后新的研究热点.硅基三维集成微系统可集成化合物半导体、CMOS、MEMS等芯片,充分发挥不同材料、器件和结构的优势,可实现传统组件电路的芯片化、不同节点逻辑集成电路芯片...     

射频三维微纳集成技术

后摩尔时代，半导体技术的发展主要有延续摩尔（More Moore）和超越摩尔（More than Moore）两条路径，延续摩尔通过新材料新范式，沿着摩尔定律进一步将线宽逐渐微缩至3 nm甚至进入埃（?）量级，超越摩尔则是采用异质异构三维微纳集成的途径来满足下一代电子高速低功耗高性能的需求。异质异构集成可以充分利用不同材料的半导体特性使得系统性能最优化。射频三维微纳集成技术推动高频微电子从平面二维向三维技术突破，成为后摩尔时代高频微电子发展的重要途经。射频三维微纳异质异构集成技术利用硅基加工精度高、批次一致性好、可以多层立体堆叠等特点，不断推动无源器件微型化、射频模组芯片化、射频系统微型化技术发展。本文介绍了射频三维微纳技术发展趋势，并给出了国内外采用该技术开拓RF MEMS器件、RF MEMS模组以及三维射频微系统技术发展和应用案例。     

高集成度X波段1W单通道硅基三维集成器件

南京电子器件研究所基于自有的8寸硅基射频微系统工艺线,研制了一款工作在X波段输出功率1W的高集成度单通道硅基三维集成器件.该器件以高阻硅为原材料,结合TSV转接板、晶圆级键合、高密度RDL以及多层BGA POP等三维集成工艺技术,在8.5 mm × 8.5 mm × 3.0mm的体积内实现了GaAs多功能芯片、收发电源...     

基于异构集成技术的相控阵T/R组件微系统

基于硅基微电子机械系统(MEMS)工艺和三维异构集成技术,研制了一款硅基X波段2×2相控阵T/R组件.该组件采用收发一体多功能芯片方案,将所有器件封装于两层硅基中.其中上层硅基集成了低噪声放大器、功率放大器、开关、电源调制驱动器和PMOSFET等芯片,下层硅基集成了多功能芯片、串/并转换芯片以及逻辑运算芯片;两层硅基封装之间通过植球进行堆叠.最终样品尺寸仅为20 mm×20 mm×3 mm.实测结果显示,在8～ 12 GHz内,该T/R组件饱和输出功率约为29 dBm,接收增益约为21 dB,接收噪声系数小于3 dB,在具备优良射频性能的同时实现了组件的小型化.     

硅基晶圆级封装的三维集成X波段8通道变频模块

<正>南京电子器件研究所将CMOS芯片、GaAs多功能芯片、硅基IPD芯片、TCSAW滤波器等多种工艺制程的芯片异构集成到硅基晶圆上,再采用TSV、微凸点以及晶圆低温键合等工艺在国内首次实现了基于硅基射频微系统集成工艺的三维集成微波模块。如图1所示,该模块包含了接收多功能、8通道滤波、镜像抑制混频多功能、中频多功能以及三种中频带宽可切换功能的集成。图2所示为射频微系统集     

射频微系统集成技术

射频系统在电子战及5G通讯等方面具有广阔的应用前景,在电子设备小型化趋势推动下,射频系统在不断提升性能的同时逐步缩减体积、降低成本.射频系统与三维集成技术相结合在研制高性能、微型化及低成本射频微系统方面具有巨大潜力.综述了射频微系统集成技术,包括多芯片集成技术、SoC集成技术、单片异质异构集成技术及基于Chiplet的...     

硅基射频微系统三维异构集成技术

<正>南京电子器件研究所根据射频组件芯片化的发展趋势,在国内首先提出了硅基射频微系统架构,在203.2 mm(8英寸)硅晶圆上,建立起了TSV射频转接板的设计/工艺能力,通过基于TSV射频转接板的三维异构集成先进工艺技术,制备出硅基首款38 GHz异构集成收发芯片,研制出4层硅片堆叠集成的X波段硅基变频芯片,形成了1.0版本的射频微系统工艺规则和多用户流程能力。TSV尺寸(30:200)μm,可以支持4层硅片的圆片级堆叠。该工艺架构在DC-40 GHz的微波性能已通过了验证。     

硅基异质集成化合物半导体技术新进展

随着摩尔定律即将走向尽头,以及军民电子信息系统对多功能集成、高密度集成、小体积重量、低功耗、大带宽、低延迟等性能的持续追求,将多种化合物半导体材料体系(如GaN、InP、SiC等)的功能器件、芯片,与CMOS集成电路的芯片进行异质集成的技术正在拉开序幕,将在微电子、光电子等领域带来一场新的革命,硅基异质集成也被认为是发展下一代集成微系统的技术平台。本文梳理了射频微电子学与硅光子学领域中以化合物半导体为主的材料(或芯片)与硅半导体材料(或芯片)异质集成的最新进展,以期国内相关领域研究人员对国外的进展有一个比较全面的了解。     

毫米波三维异质异构集成技术的进展与应用

三维异质异构集成技术是实现电子信息系统向着微型化、高效能、高整合、低功耗及低成本方向发展的最重要方法,也是决定信息化平台中微电子和微纳系统领域未来发展的一项核心高技术。文章详细介绍了毫米波频段三维异质异构集成技术的优势、近年来的发展趋势以及面临的挑战。利用硅基MEMS 光敏复合薄膜多层布线工艺可实现异质芯片的低损耗互连,同时三维集成高性能封装滤波器、高辐射效率封装天线等无源元件,还能很好地处理布线间的电磁兼容和芯片间的屏蔽问题。最后介绍了一款新型毫米波三维异质异构集成雷达及其在远距离生命体征探测方面的应用。     

硅基光电子工艺中集成锗探测器的工艺挑战与解决方法

<正>锗探测器是硅基光电子芯片中实现光电信号转化的核心器件。在硅基光电子芯片工艺中实现异质单片集成高性能锗探测器工艺，是光模块等硅基光电子产品实现小体积、低成本和易制造的优先选择。本文讨论了硅基光电子芯片集成锗探测器在实际工艺中遇到的挑战和解决思路。硅基光电子芯片集成锗探测器主要挑战在于热预算兼容、金属污染防控及工艺结构的匹配三个方面。     

片上雷达技术研究进展及发展趋势

本文回顾和梳理了当前片上雷达(Radar on Chip, RoC)的架构和射频前端、天线及信号处理等芯片化研究进展,以及基于异质异构集成、3D先进封装技术的雷达系统集成实现方案。在此基础上,从物理形态、实现工艺及技术发展等方面对片上雷达未来发展趋势进行了分析,指出基于硅基半导体工艺,片上集成多路雷达收发前端、波形产生及信号处理等雷达功能单元,实现片上系统（System on Chip, SoC）;或者通过异质异构及先进封装技术,将高度集成的雷达芯片集成在一个封装内,实现封装系统（System in Package, SiP）,从而满足雷达系统微型化、轻重量、低成本和低功耗的发展需求。同时,基于芯片化可扩充多通道阵列模块也有望构建大型复杂阵列雷达系统。该方案为未来小型化武器装备提供有效的探测感知手段,也为蓬勃发展的民用雷达提供可行的技术路径。     

一种Ka频段高密度高集成瓦式T组件的设计

介绍了一种Ka频段瓦式T组件的设计方法和关键技术.采用多层印制电路板(Printed Cir-cuit Board,PCB)技术,实现了无源网络和馈电网络集成在同一块多层电路板上,滤波功能层和天线一体化集成,利用毛纽扣实现了组件的三维垂直互联.采用互补金属氧化物半导体(Complementary Metal Oxide...     

Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons

Because of fabrication compatibility to current semiconductor technology, three-dimensional integrated circuits (3D-ICs) offer promising near-term solutions for maintaining Moore’s Law. 3D-ICs proffer high system speeds, massively parallel processing, low power consumption, and their high densities result in small footprints. In this paper, a novel 3D neuromorphic IC architecture which combines monolithic 3D integration and a synaptic array based on vertical resistive random-access memory structure (V-RRAM) is proposed. To analyze the electrical characteristics of the proposed synaptic array, a concise equivalent circuit model of the system is developed, and analytical calculations for each parameter of the equivalent circuit are provided. Moreover, a novel signal intensity encoding neuron design that can directly convert analog signal into a spiking waveform sequence is proposed and analyzed. A feasible 3D neuromorphic computing architecture is demonstrated. Applying the monolithic 3D integration technology on neuromorphic computing system hardware implementation can reduce the power consumption by 50%, and shrink die areas by 35%.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

The package integration of RF-MEMS switch and control IC for wireless applications

The integration of microelectromechanical systems (MEMS) switch and control integrated circuit (IC) in a single package was developed for use in next-generation portable wireless systems. This packaged radio-frequency (RF) MEMS switch exhibits an insertion loss under -0.4 dB, and isolation greater than -45 dB. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or field effect transistor (FET) switches and consumes less power. The RF MEMS switch chip has been integrated with a high voltage charge pump plus control logic chips into a single package to accommodate the low voltage requirements in portable wireless applications. This paper discusses the package assembly process and critical parameters for integration of MEMS devices and bi-complementary metal oxide semiconductor (CMOS) control integrated circuit (IC) into a single package.     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design

Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance.     

A CMOS analog-digital audio processor for a portable radiotelephone

A mixed analog-digital (A/D) integrated circuit (IC) specifically designed to realize the audio processing functions needed for a portable radiotelephone (PRT) application is described. Multirate signal processing techniques are used to reduce the capacitance spread, and hence the overall silicon area, of the chip, as well as to minimize the settling requirements of the amplifiers for lower power consumption. This, together with programmable power-saving control circuitry also incorporated on-chip, considerably extends the lifetime of the battery. A semicustom design methodology is employed to implement such an application-specific integrated circuit (ASIC) in a 3-μm CMOS double-poly processing technology. Experimental results are presented to demonstrate the correct operation and functionality of the prototype chips