海明码纠错的FPGA实现

对于采用海明码纠错的系统采说，提高纠错效率和可靠性对于提高数据传输速度和质量是很重要的，采用基于FPGA硬件设计的海明码纠错系统可以达到这一效果，分别从发送方海明码的生成和接收方纠错解码两方面详细阐述了该系统的实现原理，并给出了相应的Modelsim仿真时序波形图。     

基于FPGA的红外镜头自动聚焦技术研究与实现

自动聚焦技术在红外热像仪监控领域有着非常重要的作用.目前业内红外自动聚焦技术存在聚焦成功率低、架构复杂、聚焦速度慢等状况,为此提出了一种基于FPGA的红外镜头自动聚焦技术,采用单FPGA实现了红外图像处理显示和自动聚焦的功能.鉴于红外图像普遍存在竖条纹噪声和随机噪声等特点,本文在实现聚焦过程中对红外清晰度评价算法和爬山...     

基于现场可编程门阵列的高性能红外热成像系统

探讨了红外成像系统实时信号处理算法、硬件结构等关键技术.提出了一种新的自适应两点非均匀性校正(ATPC)算法,该算法以快门为目标场景来实时更新校正参数,能有效克服红外焦平面阵列(IRFPA)响应随时间漂移导致的两点非均匀性校正算法失效问题.采用查找表结构来实现平台直方图均衡(PE)算法,并对PE算法进行了优化,降低了运算量和存储空间需求.硬件系统采用两片同步动态随机存储器(SDRAM)的乒乓缓存结构,在单片现场可编程门阵列(FPGA)上实现了IRFPA的ATPC和PE算法的并行操作.实验结果表明,对320×240的IRFPA,在50 MHz系统时钟下,帧频为60 Hz时系统工作良好,处理后的红外图像质量有了明显改善,系统结构简单便于小型化,能够满足实时动态检测及追踪需求.     

用于可编程器件的MTM反熔丝特性研究

基于ONO（Oxide-Nitride-Oxide）和MTM（Metal-to—Metal）反熔丝技术的可编程存储及逻辑器件已经广泛应用于空间技术中。MTM反熔丝以其单元面积小、集成度高、反熔丝电容小和编程后电阻小等优势,更加适合深亚微米集成电路。文章通过制备MTM反熔丝单元,对单元的击穿特性和漏电性能展开研究,给出了反熔丝单元漏电流与单元尺寸的关系,对单元的编程电流和编程后的电阻值关系进行了研究,与文献[1]给出的Ron=Vf/Ip的关系基本一致。     

1kb超高速内容联想存储器的设计

超高速内容联想存储器（ＣＡＳＭ）是一种将ＲＡＭ和ＣＡＭ功能集于一体的特种存储器，分析了ＣＡＳＭ存储单元的结构，分别阐述了顺序写，顺序法，联想写和联想读四种工作模式下的工作原理，最后给出了优化设计和模拟结果。     

现场可编程滤波器阵列单元

通过对通用数字滤波器公式的细致分析，建立了一种最为精简实用的滤波器模块单元，给出了模拟结果，进而提出了编程滤波器阵列单元的概念，提供了在实用数字滤波的具体实现中比数字信号处理（ＤＳＰ）更直接，更高效的途径。     

Design and Implementation of a Field Programmable CRC Circuit Architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.      

现场可编程门阵列的供电

现场可编程门阵列（FPGA）是一种可编程逻辑器件,由成千上万个完全相同的可编程逻辑单元组成,周围是输入,输出单元构成的外设。制造完成后,FPGA可以在工作现场编程,以便实现特定的设计功能。典型设计工作包括指定各单元的简单逻辑功能,并选择性地闭合互连矩阵中的一些开关。为确保正常工作,     

激光测高仪中基于现场可编程门阵列的高精度飞行时间测量

设计了在激光测高系统中基于单芯片现场可编程门阵列(FPGA)的高精度时间间隔测量模块。该模块采用高频计数器实现粗时间测量,差分延时线内插技术完成细时间测量,时间分辨率为300 ps。该芯片同时还集成了时序切割电路、回波脉宽测量和数据传输模块等。在环境温度20℃时对该测量模块进行精度测试,获得标准偏差为94.68 ps,转换成距离为1.42 cm。最后通过地面检测,整个系统在500 km范围内的一般条件下可获得测高精度±50 cm。     

A Current Conveyor based Field Programmable Analog Array

An approach for designing a Field Programmable Analog Array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An Analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. Analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.     

DPAD2—A Field Programmable Analog Array

DPAD2 is a Field Programmable Analog Array (FPAA) based on CMOS switched capacitor technology. This paper describes the major design decisions that went into creating DPAD2 with respect to the ultimate goal of the work, being a mixed signal field programmable silicon solution. Two major compromises exist in the design of an FPAA, one between flexibility and performance, the other between functionality and die size; DPAD2 overcomes the first with a novel field programmable hierarchic routing scheme and the second by careful analysis of many disparate designs to arrive at a best compromise solution. Results from prototype silicon are presented where a single analog cell is reconfigured to perform a number of different analog signal processing functions. Bandwidth of the DPAD2 device is 500 kHz and the SNR is typically 60 dB, although both are application dependent. Introduction of the FPAA now enables a designer to have working silicon within one day, by a simple configuration of the silicon chip via a PC parallel interface. Software libraries of analog circuits are provided and allow very rapid creation of large and complex analog circuits.     

可编程模拟技术以不变应万变

FPGA等数字电路的可编程技术已在广泛应用,而模拟电路与编程通常"搭不上边儿".总部设于美国硅谷的一家新创公司Anaiggm却想出了对模拟电路进行编程的新方法,并且已有配套的硅片和编程软件问世.     

Application of Global Dynamic Reconfiguration in Artificial Neural Network System based on Field Programmable Gate Array

Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array （FPGA）. Discussed are the dynamic reconfiguration principles and methods. Proposed is a global dynamic reconfiguration scheme using Xilinx FPGA and platform flash. Using the revision capabilities of Xilinx XCF32P platform flash, an artificial neural network based on Xilinx XC2V30P Virtex-Ⅱ can be reconfigured dynamically from back propagation （BP） learning algorithms to BP network testing algorithms. The experimental results indicate that the scheme is feasible, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably.     

FPGA设计转换

本文主要论述FPGA(现场可编程门阵列)至其它ASIC实现方式,如门阵或标准单元的设计转换;介绍了设计网表转换,网表优化途径;同时,还讨论了不同厂家FPGA设计之间的转换。提出了适用于不同工艺的转换以及同种工艺不同库之间转换的设计转换思想。     

基于FPGA的视频格式转换系统设计

针对电视制式PAL/NTSC信号输出VGA显示格式的解决办法,详细讲述了基于FPGA视频格式转换系统的设计实现。采用CycloneⅢ系列的EP3C16F484C6作为核心处理器件,实现了NTSC/PAL制式视频的解码、色空间转换（CSC）、帧速率转换和隔行逐行转换、缩放、视频DAC转换,最终实现分量R、G、B的VGA视频格式的视频输出,分辨率可达1 600×1 200@100 Hz。     

A Novel Implementation Technique of Conical Scan Radar Using A Programmable Phased Array

In radar, planar phased array antenna plays vital role in electronic scanning in the azimuth and elevation direction to the horizon. In most operations using planar phased array both the coordinates of azimuth and elevation, are steered electronically. In this paper a conceptual schematic of a phased array antenna with programmable time delay units has been presented. It is shown that by suitably exploiting the time delay matrix one can have electronic beam rotation around the target axis as required in conical scan. Thus both the elevation and azimuth motors in conical scan system are replaced by electronic scanning. Heuristically, we have selected eight consecutive points for beam rotation in a polygon shape and can also be extended almost circular shape by increasing number of array elements and phase shifter (delays) in the delay matrix. The array requires dual control of phase gradient and individual phase values. The whole array is controlled by micro-controller. This presents exciting possibilities in radar operation.     

层次式布线资源FPGA连线开关的设计

提出了一种层次式布线资源FPGA连线开关的设计方法,采用迷宫算法,对连线开关的结构进行了分析.针对连线连接盒CB(connection box),提出了较为节省芯片面积的半连通结构;针对连线开关盒SB(switch box),在给出连通度fs概念后,提出了使SB连通能力达到最大值的设计方法,并通过数学推导予以证明.应用这种设计方法,设计了一种fs＝3的SB;成功地实现了采用这种结构的SB和半连通CB作为连线开关的FPGA芯片FDP-100K.该芯片在电路布通率和芯片面积方面取得了较好的平衡结果.     

Kestrel: A Programmable Array for Sequence Analysis

Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, a multiplier and efficient communication using shared registers. This paper describes Kestrel's functional units in detail, and examines each of their effects on system performance. With functional prototype chips completed, we will assemble a full single-board Kestrel array, with 512 processing elements on eight chips, in early 1998.     

Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array

In this paper, analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex（OFDM） system, and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms. Based on the analysis of coarse and elaborate synchronization algorithms, multiplexed are, the module accumulator, division and output judgement, which can evidently save the hardware resource cost. The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.