合并互补BiCMOS集成电路的研究

分析了几种常规ＢｉＣＭＯＳ门电路的特性，对合并互补（ＭＣ）ＢｉＣＭＯＳ集成电路的二输入与非门和１１级环形振荡器进行了实验研究，并与常规ＢｉＣＭＯＳ进行了比较。实验结果说明，ＭＣＢｉＣＭＯＳ具有电路结构简单，芯片面积小，工作速度高，负载能力强和低压工作特性好等优点。     

高速BiCMOS工艺研究

研究开发了一种准２μｍ高速ＢｉＣＭＯＳ工艺，采用自对准双埋双阱及外延结构．外延层厚度为２．０～２．５μｍ，器件间采用多晶硅缓冲层局部氧化（简称ＰＢＬＯＣＯＳ）隔离，双极器件采用多晶硅发射极（简称ＰＳＥ）晶体管．利用此工艺已试制出ＢｉＣＭＯＳ２５级环振电路，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｐｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力为０．６２ｎｓ／ｐＦ．明显优于ＣＭＯＳ门．     

具有优良性能的MCBiCMOS IC结构

本文分析了几种常规ＢｉＣＭＯＳ门电路的特性，对ＭＣＢｉＣＭＯＳ集成电路结构的二输入与非门和１１级环形振荡器进行了实验研究，并与常规ＢｉＣＭＯＳ进行了比较。实验结果说明：ＭＣＢｉＣＭＯＳ具有电路结构简单；芯片面积小；工作速度高，负载能力强和低压工作性能好等优点。     

高速BiCMOS工艺研究

研究开发一种准２μｍ高速ＢｉＣＭＯＳ工艺，该工艺采用乍对准双埋双阱及外延结构。外延层厚度２．０－２．５μｍ，器件间采用多晶硅缓冲层局部氧化隔离，双极器件采用多晶硅发射极晶体管。利用此工艺试制出ＢｉＣＭＯＳ２５级环振，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｑｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力 ０．６２ｎｓ／ｐＦ，明显ＣＭＯＳ门。     

采用混合模式晶体管(BMHMT)构成低温BiCMOS集成电路

本文介绍采用与ＣＭＯＳ工艺完全相容的双极／ＭＯＳ混合模式晶体管（ＢＭＨＭＴ）构成新型的低温ＢｉＣＭＯＳ集成电路．理论分析表明该电路与ＣＭＯＳ相比，在电压摆幅相同，静态功耗相近的条件下，具有更大的驱动能力，尤其在较低的工作电压下，其特点更加突出．我们用统一的标准和相同芯片面积设计了３９级带负载的ＢｉＣＭＯＳ和ＣＭＯＳ环形振荡器．实验样品经室温和低温平均门延迟时间测试，表明在相同工作电压下ＢｉＣＭＯＳ优于ＣＭＯＳ．若两种电路都采用ＳＯＩ结构，预计ＢｉＣＭＯＳ可以获得更好的结果     

高性能BiCMOS制造技术及I/O电路优化

本文报导一套先进的ＢｉＣＭＯＳ集成电路制造技术，建立在ＣＭＯＳ工艺基础上的ＢｉＣＭＯＳ制造工艺，增加了双埋层，２．５微米本征外延层，双阱，基区，多晶硅发射区，深集电区和平坦化双层金属布线等工艺技术。器件性能测试和扫描电镜检查结果表明，双极器件和ＭＯＳ器件性能优良，ＢｉＣＭＯＳ器件的抗锁定性能比ＣＭＯＳ器件提高了一个数量级。     

MCBiCMOS门阵列的母片设计

本文介绍ＭＣＢｉＣＭＯＳ门阵列的母片设计技术。由于采用了先进的ＭＣＢｉＣＭＯＳ工艺和设计技术，ＭＣＢｉＣＭＯＳ更适合地制作高性能，大规模的专用集成电路。在２μｍＣＭＯＳ和３μｍ双极相结合的设计规则基础上，我们设计了ＭＣＢｉＣＭＯＳ２０００门门阵列母片，并利用ＭＣＢｉＣＭＯＳ宏单元库，成功地完成了ＣＧＢ２００３     

发展中的BiCMOS技术

集ＣＭＯＳ与双极器件之优点于一体的ＢｉＣＭＯＳ，将逐渐成为９０年代ＵＬＳＩ的主流技术。本文从工艺、器件结构和兼容设计等不同侧面，阐述了ＢｉＣＭＯＳ技术所具有的突出特点及其典型应用，同时还介绍了最新发展的低温ＢｉＣＭＯＳ技术和面临的关键问题。     

自对准外延CoSi_2源漏接触CMOS器件技术

ＣＯ／Ｔｉ／Ｓｉ或ＴｉＮ／Ｃｏ／Ｔｉ／Ｓｉ多层薄膜结构通过多步退火技术在Ｓｉ单晶衬底上外延生长ＣｏＳｉ２薄膜，ＡＥＳ、ＲＢＳ测试显示ＣｏＳｉ２薄膜具有良好均匀性和单晶性．这种硅化物新技术已用于ＣＭＯＳ器件工艺．采用等离子体增强化学汽相淀积（ＰＥＣＶＤ）技术淀积氮氧化硅薄膜，并用反应离子刻蚀（ＲＩＥ）技术形成多晶硅栅边墙．固相外延ＣｏＳｉ２薄膜技术和边墙工艺相结合，经过选择腐蚀，可以分别在源漏区和栅区形成单晶ＣｏＳｉ２和多晶ＣｏＳｉ２薄膜，构成新型自对准硅化物（ＳＡＬＩＣＩＤＥ）器件结构．在Ｎ阱ＣＭＯＳ工艺     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极的速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主。因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ技术显得愈发相似。本文例举了０．８μｍ和０．５μｍ的技术论点，ＢｉＣＭＯＳ电路与ＣＭＯＳ相比，成本稍有增加，但其性能提高一倍。     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

Optimal usage of CMOS within a BiCMOS technology

The comparison of CMOS to BiCMOS often seen in the literature shows the delays of single-stage circuits driving a capacitive load, with the BiCMOS circuit exhibiting a bold advantage. This comparison is misleading, and it suggests that the highest possible performance chip design implemented in a BiCMOS technology, should use only BiCMOS circuits. When multistage circuits and chip wiring resistance are also considered, CMOS performance is found to be much closer to BiCMOS performance. CMOS circuits are shown to be preferred over BiCMOS circuits for a significant fraction of the chip nets. When nets that can afford a performance decrease are relaxed by using CMOS circuits instead of BiCMOS circuits, the CMOS fraction increases further. High usage of CMOS is desirable for area and yield considerations. Evaluations of the optimal CMOS role in future-generation BiCMOS technologies are expected to show an even larger role for CMOS     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

Low-operating-voltage integrated silicon light-emitting devices

A solution is presented for the fabrication of low-voltage, low-power (<4.25 V and <5 mW) silicon light-emitting devices (Si-LEDs), utilizing standard very large scale integration technology without any adaptation. Accordingly, they can be integrated with their signal processing CMOS and BiCMOS circuits on the same chip. This enables the fabrication of much needed all-silicon monolithic optoelectronic systems operated by a single supply. The structural details of two distinctly different line-patterned Si-LEDs are presented, composed of heavily doped n/sup +/p/sup +/ junctions, made by BiCMOS n/sup +/ sinker and PMOS p/sup +/ source/drain doped regions, respectively. Using this approach, other Si-LED structures can be designed to yield low- or high-voltage Si-LED operation as well. Light is emitted at low reverse bias as a result of quantum transitions of carriers, generated by field emission, as indicated by the low reverse breakdown voltage V/sub B/, the soft "knee" I-V characteristics and the negative temperature coefficient of V/sub B/. The optical performance data show that, at low reverse operating current I/sub R/, the overall emitted light intensity L is a nonlinear function of I/sub R/ and becomes linear at higher I/sub R/. A bell-shaped light spectrum is obtained, with an enhanced short wavelength and attenuated long-wavelength radiation, relative to that of avalanche Si-LEDs.     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted     

Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits

Over the last decade, SiGe HBT BiCIMOS technology has matured from a laboratory research effort to become a 50/65-GHz fT/fmax silicon-based 0.5-μm BiCMOS production technology. This progress has extended silicon-based production technology into the multigigahertz (multi-GHz) and multigigabits-per-second (multi-Gb/s) range, thus, opening up an array of wireless and wired circuit and network applications and markets. SiGe circuits are now being designed in the same application space as GaAs MESFET and HBTs, and offer the yield cost, stability and manufacturing advantages associated with conventional silicon fabrication. A wide range of microwave circuits have been built in this technology including 5.8-GHz low-noise amplifiers with 1-V supply, up to 17-GHz fully monolithic VCOs with excellent figures of merit, high-efficiency 2.4-GHz power devices with supply voltage of 1.5 V, and move complicated functions such as 2.5/5.0-GHz frequency synthesizer circuits as well as 10/12.5-Gb/s clock and data recovery PLLs. This paper focuses on several key circuit applications of SiGe BiCMOS technology and describes the performance improvements that can be obtained by its utilization in mixed-signal microwave circuit design. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBTs with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications     

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design     

CMOS-compatible lateral bipolar transistor for BiCMOS technology.II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors