A Digital Hybrid Transmission System for 280 Mbits/s and 560 Mbits/s

This paper presents the development of repeaters and line equipment for an experimental digital long-haul transmission system using coaxial cable. A comparison, of different types of digital transmission systems indicates that the digital repeater hybrid system with binary transmission code is the most desirable. This development has resulted in digital pulse reshaping repeaters with very small dimensions, low cost, and good reliability. Both digital repeaters that are without timing and regenerators that include timing have been developed. Their circuitry and the corresponding signal shapes are described. The dc power-feeding system and the fault-location system are also discussed. An experimental field trial with the Deutsche Bundespost was performed over 10-repeater sections of the International Telephone and Telegraph Consultative Committee (CCITT) normal coaxial tube with a section length of 1/2 mi, The experiments confirmed that a long-haul digital transmission system of 560 Mbits/s, and later of 1100 Mbits/s using the described system concept and technology, can be established with relatively low cost and good reliability.     

A mixed-signal BiCMOS front-end signal processor for high-temperature applications

A mixed-signal ASIC that implements an ultrasound front-end receiver in a 0.6 /spl mu/m BiCMOS HotASIC technology that features metal/metal capacitors and poly1/poly2 resistors is described. The ASIC includes a low-noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), and a second-order sigma-delta modulator (SDM), and is the most compact system for high-temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200 kHz to 700 kHz) from an ultrasound transducer. At 48 MHz clock frequency and 200/spl deg/C, the power consumption is 85 mW from a single 5 V supply. The die area of the chip is 5.52 mm/sup 2/.     

An Experimental 648 Mbits/s HDTV Digital VTR

One of the most sought-after improvements in HDTV equipment is better VTR picture quality. A promising way to achieve this is through digital recording, which is free from picture quality degradation in the recording and playback processes.     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

Adaptive analog IF signal processor for a wide-band CMOS wirelessreceiver

An IF strip for a wireless receiver supports a variable baud rate by changing analog filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV/√Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

Integrated sensor and range-finding analog signal processor

The authors present experimental results from an array of cells, each of which contains a photodiode and the analog signal-processing circuitry needed for light-stripe range finding. Prototype circuits were fabricated through MOSIS in a 2-μm CMOS p-well double-metal, double-poly process. This design builds on some of the ideas that have been developed for ICs that integrate signal-processing circuitry with photosensors. In the case of light-stripe range finding, the increase in cell complexity from sensing only to sensing and processing makes the modification of the operational principle of range finding practical, which in turn results in a dramatic improvement in performance. The IC array of photosensor and analog signal processor cells that acquires 1000 frames of light-stripe range data per second-two orders of magnitude faster than conventional light-stripe range-finding methods. The highly parallel range-finding algorithm used requires that the output of each photosensor site be continuously monitored. Prototype high-speed range-finding systems have been built using a 5×5 array and a 28×32 array of these sensing elements     

64 kbit/s audio signal transmission approaches using 32 kbit/sADPCM channel banks

Two simple 64-kb/s wideband coding approaches using 32-kb/s ADPCM (adaptive digital pulse-code modulated) channel banks are proposed and compared to CCITT 64 kb/s ADPCM, which is being recommended as CCITT G.722. These two, folding ADPCM and QMF ADPCM, are intended to pave the way for smooth transition from conventional 4-kHz band telephone systems to 7-kHz wideband systems in private networks. The first approach, supporting the high-quality audio program transmission, requires only samplers and multiplexers at the input and output ports of the channel banks. In the second approach, samplers and multiplexers are replaced by quadrature mirror filters in order to increase coding quality. Performance test results for audio signal transmission show that these simplified approaches provide an inexpensive way to introduce wideband communication systems     

An Experimental 560 Mbits/s Repeater with Integrated Circuits

The bandwidth penalty of digital systems is very obvious in the case of transmission over coaxial cables because of the exponential increse of cable attenuation with square root of frequency. From capacity point of view, it is only at very high information rates (> 500 Mbit/s typically) that a digital system might be competitive with an analog system, because the disadvantage of noise accumulation in an analog system ultimately cancels the bandwidth penalty of the digital system. In addition, it is, however, difficult to realize common functions, such as amplification, equalization, regeneration, clock extraction, etc. with electronic components having a frequency range comparable to the frequency range of the information signal, which extends from zero frequency to the microwave range. Besides, the complexity of a regenerative repeater should be kept to a minimum for reliability reasons. It is shown in the paper that with present-day technology a 560 Mbit/s repeater can be constructed, operating in sections of 1.5 km coaxial cable (2.6/9.5 mm). Also, we demonstrate that new technologies exist which may lead to repeaters with a high degree of monolithic integration, even at such a speed, which is important from the reliability viewpoint. The constructed and described repeater is characterized by unconventional and economic design of amplifier/equalizer and clock extractor and by monolithically integrated decision circuits.     

An analog CMOS front-end for a D2-MAC TV decoder

This paper describes the analog front-end of a fully integrated CMOS TV decoder, suitable for the reception of terrestrial as well as satellite signals, based on the D2-MAC transmission system. While the video reconstruction is undertaken using DSP, the front-end subsystem incorporates many linear and non-linear analog functions, including amplitude measuring, AGC, clamping, data slicing, clock recovery and of course, A/D conversion for the MAC signal processing. The chip is fabricated in 1-μ CMOS, and operates from a single 5-V supply     

A 1-V analog CMOS front-end for detecting QRS complexes in a cardiac signal

A low-voltage low-power signal processing chip for electrocardiogram measurements has been designed and manufactured. The circuit includes a continuous time, offset-compensated preamplifier with an amplification of 40 dB, an eighth-order Butterworth switched-opamp switched-capacitor (SO-SC) filter with a passband of 8-30 Hz, a 32-kHz crystal oscillator, an SO-SC postamplifier, and a bias circuit. The whole circuit operates with supply voltages from 1.0 to 1.8 V and the measured average current consumption is only about 3 /spl mu/A. The circuit is therefore very suitable for portable applications such as heart rate detectors.     

An analog drive loop for a capacitive MEMS gyroscope

The linear model and the design of an analog drive loop for the drive (primary) resonator in a capacitive gyroscope are presented. Four different types of gain control topologies are compared and analyzed with both P- and PI-type controllers. The simple model proposed in the paper allows the small signal properties of the loop to be predicted. The theoretical models based on the small signal analysis are compared to the simulated and measured results. A proportional amplitude controller, together with the rest of the drive loop, is implemented using a high-voltage 0.35-μm CMOS technology and a nominal supply of 3 V. Clock generation using a PLL and the drive loop signal as the reference are also discussed in the paper.     

A 44.736 Mbits/s Codec for U600 Mastergroups

A coder-decoder which codes a 600 channel mastergroup into a 44.736 Mbits/s digital is described. It includes a double frequency shift of the mastergroup, eight bit coding with three segment companding, and has format and features necessary for operation in a telephone network.     

An analog front-end chip set employing an electro-optical mixeddesign on SPICE for 5-Gb/s/ch parallel optical interconnection

A chip set composed of a laser-diode driver (LDD) and an optical receiver (RCV), which incorporates a full 2D (reshape, regenerate) function, has been developed by using silicon bipolar technology for a four-channel 5-Gb/s parallel optical transceiver. An electro-optical mixed design on SPICE of the LDD and the LD is accomplished by describing the rate equations of the LD as an electrical circuit. This design accommodates easy connectivity of the LDD chip to the LD in the optical transmitter module without the need for adjustment of the optical waveform. A pseudobalanced transimpedance amplifier (TIA) and feedforward automatic decision threshold control (ATC) in the RCV minimize the number of off-chip bypass capacitors, eliminate the need for any off-chip coupling capacitors, and keep crosstalk less than -50 dB and low cutoff frequency less than 80 kHz. A prototype parallel optical transmitter module and a prototype receiver module, based on the chip set, demonstrated asynchronous four-channel 5-Gb/s operation. The chip set has a throughput of 20 Gb/s with a power dissipation of 1.3 W at a 3.3-V supply     

Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor ICs

A fully integrated four-quadrant analog multiplier (4-QAM) based on switched capacitor technology is developed using a short-channel MOSFET fabrication process for realization of high-speed and high-density analog signal processor ICs. This 0.6-mm/SUP 2/ 4-QAM, consisting of a pair of MOSFETs, three op. amps., and a switched capacitor circuit, does not require any external circuits to perform the four-quadrant analog multiplication. The characteristics are measured, showing a total harmonic distortion of less than -50 dB for two input signals of 1 V/SUB p-p/, a dynamic range of more than 75 dB, and an operation speed of more than 2-MHz clock rate. In addition, the principal factors of the nonlinear distortion are analyzed. Application of the 4-QAM to convolvers and correlators is also discussed.     

Electronic-nose for detecting environmental pollutants: signal processing and analog front-end design

Environmental monitoring relies on compact, portable sensor systems capable of detecting pollutants in real-time. An integrated chemical sensor array system is developed for detection and identification of environmental pollutants in diesel and gasoline exhaust fumes. The system consists of a low noise floor analog front-end (AFE) followed by a signal processing stage. In this paper, we present techniques to detect, digitize, denoise and classify a certain set of analytes. The proposed AFE reads out the output of eight conductometric sensors and eight amperometric electrochemical sensors and achieves 91 dB SNR at 23.4 mW quiescent power consumption for all channels. We demonstrate signal denoising using a discrete wavelet transform based technique. Appropriate features are extracted from sensor data, and pattern classification methods are used to identify the analytes. Several existing pattern classification algorithms are used for analyte detection and the comparative results are presented.     

A median peak detecting analog signal processor for hard disk driveservo

An analog signal processor for hard disk drive servo is described. It performs servo demodulation by means of median peak defection which provides immunity against additive as well as multiplicative noise from the medium, unlike conventional methods. A novel circuit configuration has been employed to implement the median peak detector in an area and power efficient manner. The entire servo processor that includes the demodulator and 10 b A/D and D/A converters has been integrated into a single CMOS integrated circuit     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

An ultra-low-power programmable analog bionic ear processor

We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-microm BiCMOS technology with a power consumption of 211 microW and 77-dB dynamic range of operation. The 9.58 mm x 9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 microW power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.