Optimization of Test Wrapper for TSV Based 3D SOCs

Manufacturing of core based three-dimensional (3D) integrated circuit (IC) is an emerging field of semiconductor industry that promises greater number of devices on chip, increased performance and reduced power consumption. But due to scaling in technology features these chips are more complex. Hence testing of these 3D ICs is a challenging task and designing the test wrapper of core is also an important issue in this respect. This paper follows a IEEE 1500-style wrapper design for 3D ICs using Through Silicon Vias (TSVs) for testing purpose. It is assumed that the core elements are distributed over several layers of the ICs. As the number of available TSVs are limited due to small chip area, this work is intended to design balanced wrapper chains using minimum number of TSVs so that testing time of a core is reduced. In this work we have proposed a polynomial time algorithm of O(N) to design the test wrapper. The results are presented based on the ITC’02 SOC test benchmarks and compared with prior works. Obtained results show that our algorithm provides better utilization of TSVs compared to the work presented in Noia et al. (2011).     

用流水线技术实现STM-16帧定位电路设计

在高阶宽带电路交换专用集成电路(ASIC)芯片设计中,输入数据的帧定位和数据重排操作需要占用大量的逻辑电路.文章提出了一种流水线结构的帧定位电路设计方式,给出了STM 16码流的帧定位和数据重排的两种不同电路设计实现方案.试验结果表明,采用流水线结构设计实现的STM-16帧定位电路,可明显减小电路规模,降低芯片功耗,提高芯片的可靠性和整体性能.     

基于SOPC可重构的图像采集与处理系统设计

针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。     

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((24))2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property (IP) core for the wireless sensor node chips.     

一种基于FPGA+DSP的处理机硬件架构

为了解决在实时处理中多数合成孔径雷达(SAR)算法存在的运算量大、耗时长等问题,提出基于多核数字信号处理器(DSP)以及串行高速互联接口(SRIO)的一种新硬件解决方法。主要讨论了现场可编程门阵列(FPGA)+DSP架构下采用多核DSP和SRIO实现SAR算法的主要流程,并在多核DSP中使用流水线技术优化快速傅里叶变换(FFT)算法。通过使用多核DSP和流水线技术以及SRIO技术,使数据运算、传输速率更快,达到缩短运算时间的目的。     

Residual thermomechanical stresses in thinned-chip assemblies

A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 μm. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method     

从Matlab仿真到DSP实现信号处理算法

当用Matlab完成数字信号处理算法仿真后,如何在DSP芯片上实时实现,是电气信息类大学生需要掌握的一项重要的工程实践能力。在仿真过程中,有算法移植、DSP工程建立和算法实现这三个关键环节。本文介绍了当信号处理算法完成离线仿真后到DSP实时实现的具体步骤,并针对此过程中的常见问题,给出相应的解决方案。     

An 8-bit flash analog-to-digital converter with an array of redundant comparators

The circuit design and the topology of an 8-bit analog-to-digital converter (ADC) are presented. It is shown that the differential nonlinearity can be reduced by using three comparators and a majorizing element for formation of each bit of the thermometric code. Computer simulation and measurements of reference ADC chips fabricated using the UMC 180-nanometer CMOS technology confirmed the operability of the proposed design. A power consumption of 93 mW, an effective number of bits of 5.8, and a differential nonlinearity of 0.03 bits have been obtained     

Using GA-SVM for defect inspection of flip chips based on vibration signals

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips.     

Genetic algorithms for defect detection of flip chips

Flip chip packaging technology is widely used in high density assembly and superior performance devices. The solder joints are sandwiched between dies and substrates, leading to the defects optically opaque. Defect inspection of flip chips become more difficult. In this paper, a nondestructive detection method was presented. Ultrasonic excitations were forced on the surface of the flip chips and the raw vibration signals were measured by a laser scanning vibrometer. Eleven time domain features and twenty-four frequency domain features were extracted for analysis. After that, the genetic algorithm was introduced for feature selection and the back propagation network was adopted for classification and recognition. The flip chips were divided into three categories: good flip chips, flip chips with missing solder joints, and flip chips with open solder joints. They are recognized under the features selected by genetic algorithms rapidly and accurately, compared with those under other feature datasets, demonstrating that the approach using genetic algorithms is effective for defect inspection in flip chip packaging.     

Embedded power: a 3-D MCM integration technology for IPEM packaging application

Embedded power (EP) is the name for an integration technology for the power electronics switching stage, in which the multiple bare power chips, such as IGBTs, MOSFETs, and diodes, are buried in a ceramic frame and covered by a dielectric layer with via holes on the Al pads of the chips. Then, a planar metallization pattern is deposited onto it both for bonding to the power chips and a circuit wiring. The ceramic frame can be used as an extra thermal path and substrate for fabrication of the hybrid circuit with compatible thin- or thick-film techniques. When this integrated chips component is stacked with a base substrate and the associated components, a novel three-dimensional (3-D) multichip module (MCM) is produced. Such an integrated power electronics module (IPEM) offers performance improvement, functional integration, and process integration, as compared to conventional power hybrid modules. This paper presents the details of this technology, including the process design and implementation. A subsystem IPEM, incorporating power factor correction (PFC) and dc/dc switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized to demonstrate the feasibility of this power electronics integration technology. The capability for functional integration and the electrical performance improvement, which includes reduction in parasitics and increase in efficiency, are presented.     

T-S-T三级交换网络路径搜索算法的研究

这几年光纤通讯技术的飞速发展使得目前高速通讯网络性能的瓶颈集中在高速交换系统,研究、设计和制造高速交换系统对目前高速通讯网络具有极其重要的意义.提出一种新的三级交换的矩阵模型,在这种模型上设计无阻塞交换算法.介绍这种T-S-T网络的调度算法的实现和实验结果.算法设计和实现的过程中,大量的实验表明,该算法具有良好的特性,而且通过芯片级联可实现.     

Defect detection of IC wafer based on two-dimension wavelet transform

Defect detection of integrated circuit (IC) wafer based on two-dimension wavelet transform (2-D DWT) is presented in this paper. By utilizing the characteristics many of the same chips in a wafer, three images with defects located in the same position and different chips are obtained. The defect images contain the standard image without any defects. 2-D DWT presented in the paper can extract the standard image from the three defect images. The algorithm complexity of the method is close to that of 2-D DWT. After obtaining the standard image, the speed and accuracy of defects detection can be greatly enhanced using the detection method presented in the paper. Using the image gray-scale matching technology, impact of illumination on IC defect detection is solved. Experiments demonstrate that 2-D DWT is fast and accurate to defects detection in an IC image, and the method has high robustness for illumination.     

A very fast multiplication algorithm for VLSI implementation

We present a simple recursive algorithm for multiplying two binary N-bit numbers in parallel O(log N) time. The simplicity of the design allows for a regular layout. The area requirement of this algorithm is comparable with that of much slower designs classically used in monolithic multipliers and in signal processing chips, hence the construction has definite practical impact.     

Cell-based interconnect migration by hierarchical optimization

Fueled by Moore's Law, VLSI market competition and economic considerations dictates the introduction of new processor's microarchitecture in a two-year cycle called “Tick-Tock” marketing strategy. A new processor is first manufactured in the most advanced stable process technology, followed in a one-year delay by introducing chips comprising same microarchitecture but manufactured in a newer scaled process technology, thus allowing higher production volumes, better performance and lower cost. Tick-Tock is enabled by the automation of chip's layout conversion from an older into a newer manufacturing process technology. This is a very challenging computational task, involving billions of polygons. We describe an algorithm of a hierarchy-driven optimization method for cell-based layout conversion used at Intel for already several product generations. It transforms the full conversion problem into successive problems of significantly smaller size, having feasible solutions if and only if the full-chip problem does. The proposed algorithm preserves the design intent, its uniformity and maintainability, a key for the success of large-scale projects.     

APC-AB codec modules operating at 16 and 8 kbit/s

High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm×50 mm×12 mm, and its typical power consumption is 500 mW using 2-μm CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit μ-law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems)     

High density interconnects and flexible hybrid assemblies foractive biomedical implants

Advanced microtechnologies offer new opportunities for the development of active implants that go beyond the design of pacemakers and cochlea implants. Examples of future implants include neural and muscular stimulators, implantable drug delivery systems, intracorporal monitoring devices and body fluid control systems. The active microimplants demand a high degree of device miniaturization without compromising on design flexibility and biocompatibility requirements. With the need for integrating various microcomponents for a complex retina stimulator device, we have developed a novel technique for microassembly and high-density interconnects employing flexible, ultra-thin polymer based substrates. Pads for interconnections, conductive lines, and microelectrodes were embedded into the polyimide substrate as thin films. Photolithography and sputtering has been employed to pattern the microstructures. The novel “MicroFlex interconnection (MFI)” technology was developed to achieve chip size package (CSP) dimensions without the requirement of using bumped flip chips (FC). The MFI is based on a rivet like approach that yields an electrical and mechanical contact between the pads on the flexible polyimide substrate and the bare chips or electronic components. Center to center bond pad distances smaller than 100 μm were accomplished. The ultra thin substrates and the MFI technology was proven to be biocompatible. Electrical and mechanical tests confirmed that interconnects and assembly of bare chips are reliable and durable. Based on our experience with the retina stimulator implant, we defined design rules regarding the flexible substrate, the bond pads, and the embedded conductive tracks. It is concluded that the MFI opens new venues for a novel generation of active implants with advanced sensing, actuation, and signal processing properties     

地址数据复用型Flash存储器测试技术研究

随着半导体技术的迅猛发展,移动存储设备快速增长。Flash芯片作为移动存储设备中最常用的器件,得到了日趋广泛的应用,对Flash芯片的测试要求也越来越高。地址数据复用型Flash存储器测试技术研究及电路设计,设计改善大规模数字集成电路测试系统数字系统算法图形功能。对K9F2G08R0A进行了测试并通过对数字系统算法图形功能进行改善,算法图形发生器由多个算术逻辑单元、多路选择器以及操作寄存器组成,可以实现复杂的逻辑操作和算术运算,可以更快、更简便地对地址复用型Flash存储器进行测试,减少测试程序开发难度。     

面积优化RS编解码器的VLSI设计

介绍了一种适用于数字电视广播视频(DVB)系统的面积优化RS(204, 188)编解码器的VLSI设计.设计中,充分考虑DVB系统的特性,采用软硬件协调和优化的三级流水线结构,运用改进的Berlekamp-Massey迭代算法来实现,有效地缩小了RS编解码器的面积,适合应用于高清晰数字电视芯片.