Measurement technique for the quotient of cross sections /spl sigma//sub e/(/spl lambda//sub s/)//spl sigma//sub a/(/spl lambda//sub s/) of erbium-doped fibers

A method for the measurement of the quotient of the emission and absorption cross section of erbium-doped fibers is presented which utilizes the spontaneous emission perpendicular to the fiber axis. The maximum population of the first excited state achievable through illumination by signal light (/spl lambda//sub s/=1530 nm) is fixed by the quotient of the absorption and the emission cross section. This fact is used to determine the desired quotient. First measurements show that this method is very simple and highly accurate.<>     

Broadband 180/spl deg/ bit phase shifter using a /spl lambda//2 coupled line and parallel /spl lambda//8 stubs

In this paper, a broadband 180/spl deg/ bit phase shifter using a new switched-network was presented. The new network is composed of a /spl lambda//2 coupled line and parallel /spl lambda//8 open and short stubs, which are shunted at the edge points of a coupled line, respectively. According to a desired phase shift, it provides a controllable phase dispersive characteristic by the proper determination of Z/sub m/,Z/sub s/, and R values. The 180/spl deg/ bit phase shifter operated at 3 GHz was fabricated and experimented using design graphs which provide the required Z/sub m/,Z/sub s/ values, and I/O match and phase bandwidths. The experimental performances showed broadband characteristics.     

Protecting a power-laser diode from retroreflections by means of a fiber /spl lambda//4 retarder

A quarter-wave retarder made by a small loop of fiber on the laser pigtail is an effective means to protect the laser from retroreflections. Suppression factors of about 20 dB have been achieved with negligible insertion losses. An example of application is given. A method to measure the isolation is also presented.     

Systematic design of double-sampling /spl Sigma//spl Delta/ A/D converters with a modified noise transfer function

Double-sampling /spl Sigma//spl Delta/ analog-digital converters (ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseband. In this brief, we present a systematic design strategy for such ADCs. It consists of finding optimal pole positions for the modified NTF. This can be combined with optimizing the zeros as well. Next, we introduce several efficient structures that have enough degrees of freedom to realize the optimized pole positions.     

A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulator's noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.     

Proposed enhancement of side-mode suppression ratio in /spl lambda//4 shifted distributed feedback lasers with nonuniform diffused quantum wells

An enhancement of the side mode suppression ratio, by utilizing interdiffused quantum wells, of a /spl lambda//4 shifted distributed feedback laser is demonstrated theoretically. It is found that by introducing a diffusion step along the longitudinal direction of the quantum-well active region, the suppression ratio can be improved significantly for large /spl kappa/L (>2.6) devices. The maximum power for single longitudinal mode operation is increased by more than 50 mW.     

A direct digital frequency synthesizer with fourth-order phase domain /spl Delta//spl Sigma/ noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage /spl Delta//spl Sigma/ interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q/sup 2/ Random Walk switching scheme. The /spl Delta//spl Sigma/ interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage /spl Delta//spl Sigma/ noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-/spl mu/m CMOS technology with active area of 1.11mm/sup 2/ including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm/sup 2/. The total power consumption of the DDFS is 200mW with a 3.3-V power supply.     

Fabrication of MOD-derived YBCO films on [001]LaAlO/sub 3/ and their application to /spl lambda//4 CPW SIR BPFs

Chemically derived epitaxial thin films of YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) are fabricated on [001]LaAlO/sub 3/ substrates by the metalorganic-deposition (MOD) process, which has advantages of high quality, nonvacuum, low-cost, and large-scale production of high-T/sub c/ superconducting films. The MOD-derived YBCO films have a sharp transition at the critical temperature (90.4 K) and a high-quality film with a surface resistance of 0.13 m/spl Omega/ (30 K, 9.98 GHz) is obtained. As a microwave application, simple and compact bandpass filters (BPFs) using /spl lambda//4 coplanar-waveguide. stepped-impedance resonators are demonstrated on the YBCO films. A two-stage Chebyshev BPF of center frequency of 5.731 GHz, bandwidth of 135 MHz, and insertion loss of 0.29 dB with little input power dependency in a power range less than 10 dBm is realized on the film.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

Channel precoding with small envelope variations for /spl pi//4-QPSK and MSK over frequency-selective slow fading channels

This paper presents channel precoding schemes to combat intersymbol interference (ISI) over a frequency-selective slow fading channel in wireless communication systems using /spl pi//4 shifted quadrature phase-shift keying or minimum shift keying. Based on the dimension partitioning technique, the precoders predistort the phase of the transmitted symbol in the forward link to combat ISI, keeping the transmitted symbol amplitude constant. The proposed schemes can ensure the stability of the precoder even in equalizing a nonminimum-phase channel, combat ISI without increasing the complexity of portable unit receivers, and reduce the envelope variations of transmitted signals such that power-efficient nonlinear amplifiers can be used for the precoded signals without causing a significant undue distortion. Theoretical analysis and simulation results are presented to demonstrate the effectiveness of the proposed channel precoding schemes.     

High-speed (/spl ges/1 GHz) electrical and optical adding, mixing, and processing of square-wave signals with a transistor laser

This letter reports the common-emitter operation (gain /spl beta/=/spl Delta/I/sub C///spl Delta/I/sub B/>1, 20/spl deg/C, I/sub B/=36 mA, /spl lambda/=970 nm) of a dual-input transistor laser, arranged with a separate base contact on either side of a single emitter, that adds, mixes, and processes high-speed square-wave electrical inputs and delivers separate electrical and optical outputs. Applying a square-wave electrical input X/sub 1/(t) to one base contact and X/sub 2/(t) at a second base input, we obtain, with the pulsewidth modulated because of mixing, an electrical output proportional to /spl beta//spl times/[X/sub 1/(t)+X/sub 2/(t)] and a laser output tracking the electrical output (h/spl nu//spl times/f[X/sub 1/(t)+X/sub 2/(t)]) and exceeding it in bandwidth (pulse sharpness).     

Simple K-band MMIC VCO utilizing a miniaturized hairpin resonator and a three-terminal p-HEMT varactor with low phase noise and high output power properties

Presents a fully monolithic K-band MMIC voltage-controlled oscillator (VCO) implemented by using a 0.25 /spl mu/m AlGaAs/InGaAs pseudomorphic HEMT (p-HEMT) technology. The use of a half-wavelength miniaturized hairpin-shaped resonator and a three-terminal p-HEMT varactor was effective in reducing the chip size and simplifying fabrication processes of the microwave MMIC VCO without impairing the performance of the circuit. The VCO provides a typical output power of 11.5 dBm at 20.8 GHz and a free-running phase noise of -82 dBc/Hz at 100 kHz offset and -95 dBc/Hz at 1 MHz offset. It also shows a tuning range of 70 MHz with little reduction in output power and high yield properties. The chip size of the MMIC VCO is 1.5 /spl times/ 2.0 mm/sup 2/.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.     

A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process

A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Q/sub max/) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.     

A 6.7-fF//spl mu/m/sup 2/ bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance is proposed. BIGCAP is composed of a pair of accumulation-mode n-poly gate capacitors in an n-well and a pair of pMOS gate capacitors, which requires no additional fabrication process steps. Measured results with 1.5-V 0.13-/spl mu/m digital CMOS technology show that the intrinsic capacitance is 6.7 fF//spl mu/m/sup 2/ (6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is /spl plusmn/2.9% and capacitance variation across a wafer is as small as /spl sigma/= 0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only /spl sigma/= 0.69% and the linearity ranged from /spl plusmn/2.84% to /spl plusmn/2.93%. For three types of BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than /spl plusmn/4% linearity is achievable by optimizing the ratio (x) of the pMOS gate capacitors' area to the area of the n-poly gate capacitors, and the optimum x value is within a range of 15%-25%. BIGCAP has been applied to the loop filter of a differential phase-locked loop (PLL) and reduces the gate area of the largest loop filter capacitor to only 35% of that of the conventional design while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps (peak-to-peak) at 840 MHz with a 1.5-V supply.