Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests

This paper reports novel methods for accelerated ageing tests, with comparative reliability between them for stresses applied on power RF LDMOS: Thermal Shock Tests (TST), Thermal Cycling Tests (TCT), High Voltage Drain (HVD) and coupling thermal and electrical effects under various conditions. The investigation findings obtained after various ageing tests show the degradation and the device’s performance shifts for most important electric parameters such as transconductance (Gm), on-state resistance (R_{ds_on}), feedback capacitance (C_rss) and gatedrain capacitance (C_gd). This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. However, this is explained by excitation and trapping of electrons in the oxide-silicon interface at the drain side. A physical simulation software (2D, Silvaco-Atlas) has been used to locate and confirm degradation phenomena.     

Performance drifts of N-MOSFETs under pulsed RF life test

This paper presents a reliability life test bench specifically dedicated to high RF power devices for lifetime tests under pulse conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band test bench in operating modes. The investigation findings of degradations of critical electrical parameters derived from the data treatment after this accelerated ageing tests are presented. Numerous duty cycles are applied in order to stress Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS). It shows with tracking of a set of RF parameters (P_out, Gain and Drain Efficiency: DE) that the dominant degradation phenomenon is linked to hot carriers generated interface states (traps) and trapped electrons. Which results in a build up of negative charge at Si/SiO₂ interface and the main cause appear with incidence on RF power device. Physical simulation software (Silvaco-Atlas) has been used to locate and confirm these phenomena.     

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C–V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.     

Comparative analysis of accelerated ageing effects on power RF LDMOS reliability

We present in this paper results of comparative reliability study of three accelerated ageing tests applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test), Thermal Cycling Tests (TCT, air-air test) and High Temperature Storage Life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The results obtained show the variation and the Device’s performance quantitative shifts for some macroscopic electric parameters such as threshold voltage (V_th), transconductance (G_m), drain-source current (I_ds), on-state resistance (R_{ds_on}) and feedback capacitance (C_rs) under various ageing tests. To understand the degradation phenomena that appear after ageing, we used a new electro-thermal model implemented in Agilent’s ADS as a reliability tool.     

Reliability study of power RF LDMOS device under thermal stress

This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied to power RF LDMOS: Thermal Shock Tests (TST, air-air test) and Thermal Cycling Tests (TCT, air-air test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures ΔT). The investigation findings of electrical parameter degradations after various ageing tests are discussed. On-state resistance (R_{ds_on}) is reduced by 12% and feedback capacitance (C_rss) by 24%. This means that the tracking of these parameters enables to consider the hot carrier injection as dominant degradation phenomenon. To reach a better understanding of the physical mechanisms of parameter's shift after thermal stress, a numerical device model (2D, Silvaco-Atlas) was used to confirm degradation phenomena.     

Leakage current effects on N-MOSFETs after thermal ageing in pulsed life tests

This paper presents a synthesis of leakage current effects on N-MOSFET performances, after thermal ageing in pulsed life tests. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band bench in operating modes. It is interesting to understand the degradation mechanism effects caused by the increase leakage current and in turn on drifts of critical parameters. It shows with tracking of a set of RF parameters (Pout, Gain and Drain Efficiency: DE) that only Hot Carrier Injection (HCI) phenomenon appears with incidence on RF. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build up of negative charge at Si/SiO₂ interface. The physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations to locate and confirm these phenomena.     

Evolution study of the ElectroMagnetic Interference for RF LDMOS in series chopper application after thermal accelerated tests

The temperature is a critical parameter, for proper functioning of a system or a circuit, particularly in RF electronic devices. It considerable influence on reliability and performances; consequently plays an essential part in failure mechanisms and in lifetime. Recent studies have been focused in ElectroMagnetic Interferences (EMI) evolution after accelerated ageing tests and their effects on robustness behaviours (static, dynamic and RF). Even rarer to use RF devices in a power application.This paper deals with the (EMI) evolution of conducted interferences in common and differential mode of RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices applied to a series chopper. In addition their influences on the electrical parameters are studied after various thermal accelerated ageing tests. The experimental results (spectre and waveform parameters) are presented and discussed. The obtained measurements have highlighted that there is a clear increase in the amplitude of resonances on the interference spectra after ageing. The evolution is not the same for all the parameters and for the different thermal tests. The shift is proportional to temperature. To reach a better understanding of the physical mechanisms of parameter’s shift after thermal tests, a numerical model (Silvaco-Atlas) was employed to confirm the degradation phenomena. Actually, the charge trapping in the gate oxide causes a decrease in the Miller capacity value (C_rss), thereafter in turn a decrease in the disturbances level.     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

RF LDMOS器件与高效率功率放大器设计

为满足人们高速通信的需求,多载波、宽带已经成为新的发展方向,这对功率器件和放大器需要提出新的要求。文中基于改进后CMOS工艺模块,针对GSM基站频段,通过对RF LDMOS版图的优化,制备了实际的RF LDMOS芯片,使用负载牵引系统测出器件在940MHz时P3dB压缩点输出功率52.6dBm,效率72%。并使用负载牵引系统测量出的数据制作了一款工作于920~960MHz的高效率功率放大器,通过对匹配电路地优化,P1dB压缩点达到52.7dBm,P1dB压缩点效率为65%,在功率回退8dB时效率为32.8%,线性增益18dB。     

射频SOI LDMOS功率放大器设计与仿真

简介了改进的绝缘层上硅横向扩散金属氧化物一半导体(SOI LDMOS)电路模型.根据改进的SOI LDMOS电路模型,采用射频仿真软件进行了射频功率放大器的设计与仿真.该射频功率放大器采用两级放大结构,采用了S参数设计方法和负载牵引方法设计.结果表明放大器的增益达到15 dB,输出功率达到25 dBm,功率附加效率大于40%.     

n埋层PSOI结构射频功率LDMOS的输出特性

提出了具有n埋层PSOI(部分SOI)结构的射频功率LDMOS器件.射频功率LDMOS的寄生电容直接影响器件的输出特性.具有n埋层结构的PSOI射频LDMOS,其Ⅰ层下的耗尽层宽度增大,输出电容减小,漏至衬底的结电容比常规LDMOS和PSOI LDMOS分别降低39.1%和26.5%.1dB压缩点处的输出功率以及功率增益比PSOI LDMOS分别提高62%和11.6%,附加功率效率从34.1%增加到37.3%.该结构器件的耐压比体硅LDMOS提高了14%.     

n埋层PSOI结构射频功率LDMOS的输出特性

提出了具有n埋层PSOI(部分SOI)结构的射频功率LDMOS器件.射频功率LDMOS的寄生电容直接影响器件的输出特性.具有n埋层结构的PSOI射频LDMOS,其Ⅰ层下的耗尽层宽度增大,输出电容减小,漏至衬底的结电容比常规LDMOS和PSOI LDMOS分别降低39.1%和26.5%.1dB压缩点处的输出功率以及功率增益比PSOI LDMOS分别提高62%和11.6%,附加功率效率从34.1%增加到37.3%.该结构器件的耐压比体硅LDMOS提高了14%.     

单芯片大功率RFLDMOS晶体管设计与实验

传统射频LDMOS晶体管的源区采用重掺杂p+sinker结构,该结构会占据较大的芯片面积。文中采用槽型sinker结构,可将源区sinker面积减少1/3以上。通过流片实验,得到饱和电流为170 mA/mm、击穿电压120 V、截止频率和最大振荡频率分别为5.5 GHz和10 GHz的RF LDMOS器件。在50 V工作电压、1 090 MHz频点下栅宽345 mm单芯片器件的最大输出功率362 W,功率增益15.6 dB,漏极效率38.1%。     

一种适用于射频集成电路的抗击穿LDMOS设计

提出了一种具有深阱结构的RF LDMOS,该结构改善了表面电场分布,从而提高了器件的击穿电压。通过sil-vaco器件模拟软件对该结构进行验证,并对器件的掺杂浓度、阱宽、阱深、栅长进行优化,结果表明,在保证LDMOS器件参数不变的条件下,采用深阱工艺可使其击穿电压提升50%以上。     

硅LDMOS射频功率器件的发展历程与趋势

从芯片结构的变化以及可靠性的提升角度简述了LDMOS射频功率器件的发展历程及趋势,给出了LD-MOS的最新研制结果。现在LDMOS射频功率器件在向高工作电压、高输出功率、高可靠以及脉冲应用等方向发展。     

Analysis of punch-through breakdown in bulk silicon RF power LDMOS transistors

The design and electrical performance of bulk silicon power LDMOS transistors for base station applications are analyzed in this paper. Power LDMOS transistors have been fabricated with a seven mask levels process technology including a LOCOS oxide in the drift region and a polysilicon field plate. Specific on-state resistances in the range of 3 mΩ × cm² have been experimentally measured on fabricated LDMOS transistors with a voltage capability of 80 V and a threshold voltage around 2.5 V. Moreover, the impact of the basic geometrical and technological parameters on the voltage capability and on the on-state resistance is also analyzed. Special emphasis has been made on the existence of a premature breakdown by a punch-through mechanism due to the combination of a low Boron dose in the body region and an excessive phosphorous dose in the drift region. Technological solutions for avoiding this undesired phenomenon are also discussed.     

基于CMOS工艺的高效，高耐用性RF LDMOS器件

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively(P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3-5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.     

Wear out failure mechanisms in aluminium and gold based LDMOS RF power applications

In this paper we will compare the electromigration and hot carrier properties of the old (gold based) and new (aluminium based) metallisation schemes as used in RF base station power amplifiers manufactured by Philips Semiconductors. We will show that the latest generation shows excellent reliability performance while the RF performance has been strongly enhanced. This has been obtained by optimizing the process and device architecture. Both results of electromigration measurements on test structures and electromigration degradation of full devices will be shown. It is concluded that the latest generation LDMOS RF amplifiers shows excellent RF and reliability performance while using an aluminium based metallisation scheme.     

Influence of rapid thermal annealing on morphological and electrical properties of RF sputtered AlN films

Aluminum nitride films were deposited, at 200 °C, on silicon substrates by RF sputtering. Effects of rapid thermal annealing on these films, at temperatures ranging from 400 to 1000 °C, have been studied. Fourier transform infrared spectroscopy (FTIR) revealed that the characteristic absorption band of Al–N, around 684 cm⁻¹, became prominent with increased annealing temperature. X-ray diffraction (XRD) patterns exhibited a better, c-axis, (0 0 2) oriented AlN films at 800 °C. Significant rise in surface roughness, from 2.1 to 3.68 nm, was observed as annealing temperatures increased. Apart from these observations, micro-cracks were observed at 1000 °C. Insulator charge density increased from 2×10¹¹ to 7.7×10¹¹ cm⁻² at higher temperatures, whereas, the interface charge density was found minimum, 3.2×10¹¹ eV⁻¹cm⁻², at 600 °C.