多晶发射极结构三极管抗总剂量能力研究

文章通过分析总剂量辐照机理和三极管结构总剂量辐照的瓶颈部位,比较普通和多晶发射极VNPN晶体管结构上的区别,指出多晶发射极结构具有更强的总剂量辐照能力。多晶发射极结构总剂量辐照能力增强是由于该结构EB之间存在多晶+薄氧化层的结构,该结构中多晶屏蔽了顶部厚氧化层辐照效应的影响,而普通结构EB之间则是厚氧化层结构,总剂量辐照能力弱。在对多晶发射极结构总剂量辐照关键部位的分析过程中,对多晶发射极三极管局部结构进行了进一步优化设计,最后给出了多晶发射极结构三极管的辐照实验结果,并对实验结果进行了分析。     

多发射极条功率SiGe HBT的热电耦合与优化设计

利用自洽迭代数值计算方法,对多发射极微波功率SiGe HBT芯片热电耦合特性进行了模拟和分析。结果表明,通过对晶体管发射极条长、条间距的调整,可以有效地改善芯片温度分布的不均匀性,提高晶体管的热稳定性和功率处理能力。     

一种高速高压NPN管的研制

把Ｎｉｎｇ－Ｔａｎｇ测试发射极电阻的方法进行扩展，用来测试多晶发射极界面氧化层电阻，作发射极界面氧化层电阻与多晶硅发射极晶体管退火的优化实验，获得退火的优化工艺条件，并由此成功地研制出ＢＶＣＥＯ≥３０，ＢＶＣＢＯ＝７５Ｖ，ｆｒ＝２ＧＨｚ，β＝１８０的多晶硅发射极晶体管。用扩展电阻ＳＳＭ１５０型测多晶硅发射极晶体管的纵向杂质分布，得出多晶硅发射极晶体管的发射区结深为５０ｎｍ，基区结深为２０ｎｍ。     

多晶发射极超增益晶体管

用多晶发射极工艺制成了超增益晶体管,当I_c从1mA减小到20nA时,h_(FE)始终保持在2000左右。     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

SiGe HBT器件的研究设计

研制了一种平面集成多晶发射极SiGe HBT,并对SiGe HBT设计进行了研究分析。给出了双极晶体管的结构和关键工艺参数,并进行了流片测试,结果表明,在室温下电流增益β大于1500,最大达到3000,Vceo为5V,厄利电压VA大于10V,βVA乘积达到15000以上。这种器件对多晶Si发射极As杂质浓度分布十分敏感。     

免镇流电阻的非均匀发射极指间距设计对多指功率双极晶体管射频功率性能的改善

对不添加镇流电阻的非均匀发射极条间距的多发射极条异质结双极晶体管(HBT)的射频功率性能和表面温度分布进行了测量,并与常规采用镇流电阻的多发射极条功率HBT进行了比较.实验结果表明,对具有非均匀发射极条间距的多发射极条HBT,采用US QFI TMS红外测量系统测得的最高表面温度、温度分布均匀性以及采用射频测量系统测得...     

Bipolar技术中多晶发射极的腐蚀

在现代比较先进的Bipolar技术中,一般采用多晶发射极结构,这种结构可以提高双极管放大倍数和频率响应特性,因此,这种结构得到广泛的应用。由于这种结构中多晶是直接和硅衬底接触的,多晶腐蚀时要注意过腐蚀量、腐蚀均匀性以及腐蚀后硅衬底的形貌问题。本文主要介绍在这种工艺过程中我们进行的相关实验以及控制方法。最后,简单介绍我们工艺开发的第一批结果。     

免镇流电阻的非均匀发射极指间距设计对多指功率双极晶体管射频功率性能的改善（英文）

对不添加镇流电阻的非均匀发射极条间距的多发射极条异质结双极晶体管(HBT)的射频功率性能和表面温度分布进行了测量,并与常规采用镇流电阻的多发射极条功率HBT进行了比较。实验结果表明,对具有非均匀发射极条间距的多发射极条HBT,采用USQFITMS红外测量系统测得的最高表面温度、温度分布均匀性以及采用射频测量系统测得的射频功率增益和功率附加效率,分别低于、好于和高于具有镇流电阻的多发射极条功率HBT的情况。这些结果的取得,得益于采用非均匀发射极条间距改善了多发射极条HBT的热电正反馈和不同发射极条之间的热耦合,以及摆脱了传统HBT加镇流电阻带来的对射频功率性能的负作用。     

复合介质L型侧墙形成技术

:给出了 E- B之间复合介质 L型侧墙的形成技术。这种工艺技术控制容易 ,成品率高 ,均匀性好。已将这种工艺技术应用于双层多晶硅双极晶体管的制作工艺中 ,器件具有良好的电学特性。     

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I-V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14 V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600 V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.     

Improving collector-current uniformity in emitter-gradedAlGaAs/GaAs heterojunction bipolar transistors

To investigate the effect of a graded layer on collector-current uniformity, two types of HBTs were fabricated by metalorganic chemical vapor deposition (MOCVD). One type had a bandgap graded layer at the emitter-based interface to eliminate the conduction-band spike. The other type was a conventional HBT (heterojunction bipolar transistor) with an abrupt heterojunction fluctuated due to the fluctuation of the barrier energy from the emitter to the base. The bandgap-graded layer drastically suppressed the fluctuation of the collector current. the standard deviation of the threshold voltage was improved from 3.03 to 0.42 V by adopting bandgap grading at the emitter-based interface     

Improvement of RCA transistor using RTA annealing after theformation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 × 8 μm². The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively     

Subnanosecond emitter-coupled logic gate circuit using Isoplanar II

Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.     

用于场发射显示器的火山口型场发射阴极

介绍一种国内外研究的用于场发射显示器的火山口型场发射阴极,它相对于尖锥型场发射阴极来说，具有制作方法简单，制作成本更低，发射一致性更好，更适合大规模工业化生产。但不足之处是发射电流密度太小和有较大的栅极电流。文章详细介绍了火山口型场发射阴极的制作过程，分析并测试了其发射性能以及转移到玻璃基底上的制作方法。最后还介绍了火山口型场发射阴极的改进型-跑道型场发射阴极。     

Size dependence of the magnetic and electrical properties of thespin-valve transistor

The electrical and magnetic properties of the spin-valve transistor (SVT) are investigated as a function of transistor size. A new fabrication process, designed to study the size dependence of the SVT properties, uses: silicon-on-insulator (SOI) wafers, a combination of ion beam and wet etching and a negative tone photoresist (SU8) as an insulating layer. The Si/Pt emitter and Si/Au collector Schottky barrier height do not depend on the transistor dimensions. The parasitic leakage current of the Si/Au collector is, however, proportional to its area. The relative collector current change with magnetic field is 240%, independent of size, while the transfer ratio starts to decrease for SVTs with an emitter area below 25 × 25 μm². The maximum input current is found to be limited by the maximum current density allowed in the base (1.7 × 10⁷ A/cm²), which is in agreement with the maximum current density for spin valves     

Investigation of very fast and high-current transients in digitalbipolar IC's using both a new compact model and a device simulator

The design and optimization of high-speed integrated bipolar circuits requires accurate and physical transistor models. For this, an improved version of the compact model HICUM was developed. It is an extension of the small-signal model recently described to the large-signal (transient) case. The model, which takes into account emitter periphery and non-quasi-static (NQS) effects, is semi-physical, allowing the calculation of its elements for arbitrary transistor geometries from specific electrical and technological data. This is an important precondition for transistor optimization in a circuit and for worst case analysis. The model was verified for basic building blocks of high-speed digital circuits like emitter follower and current switch. For this, mixed-mode device/circuit simulation is used instead of measurements, since the latter would give too large errors for the fast transients of interest. It is demonstrated that-in contrast to the obsolete but frequently used SPICE Gummel/Poon model-the new HICUM is well suited for modeling very-high-speed transistor operation also at high current densities. Moreover, it is shown that at very fast transients the influence of NQS effects can no longer be neglected. As a practical application example, a high-speed E²CL circuit is simulated using the new model. The results show again that high-current models are very useful for designing IC's at maximum operating speed. This is because the optimum emitter size is often the minimum size, which is limited by high-current effects. Especially, in the case of current spikes (e.g., in emitter followers) it is difficult to find the optimum emitter size without having adequate transistor models     

高速微功耗改进型肖特基晶体管逻辑

研制了一种应用漂洗发射极晶体管和U型槽隔离技术的改进型肖特基晶体管逻辑电路(MSTL),它不仅具有标准STL高速度和ISL工艺简化的优点,与采用多晶硅发射极晶体管和氧化隔离技术的MSTL比较,进一步简化了工艺,且能在微功耗下工作.实验表明,采用4μm的设计规则,在50μA的工作电流下,传输延迟时间为3.2ns,速度功耗乘积为0.24pJ,集成度为190门/mm~2.     

Intermodulation distortion of a bipolar common-emitter amplifier with arbitrary emitter impedance and input matching network

In this paper, concise formulas for the intermodulation distortion of a bipolar common-emitter amplifier stage with arbitrary emitter impedance and input matching network are presented. These expressions provide quantitative insight in the influence of transistor properties, emitter degeneration and input power matching on distortion. Only a small set of measurable transistor parameters is needed. As examples, IIP3 is calculated for transistor only, transistor with emitter inductance, and transistor with emitter inductance and input matching circuit. Two transistors are compared: a double-poly Si transistor and a SiGe transistor in a similar process. A good agreement between analytical and numerical results is obtained.