IGBT全自动装片机工艺方法研究

IGBT全自动装片机是用于IGBT制造封装业中的后道封装工艺-固精工序。传统的封装工艺采用两台设备经过两次装片,两次加热,容易造成两次氧化的工艺、应力二次释放等问题。文章讨论的IGBT装片工艺是在一台设备上完成双芯片键合和焊料封装工序,实现IGBT器件的高速、精确装片,为了实现本工艺采用了双抓取、双Wafter平台技术,双识别、双监控系统等多项高端技术。文章从IGBT全自动装片机研究的必要性、工艺的创新性、可行性等几个方面进行了分析。     

分立IGBT的封装技术研究

文章通过对单器件的分立IGBT的封装结构进行分析,针对其结构特点和封装技术要求,特别是封装关键工艺芯片切割的影响,对装片、焊接方面进行工艺研究。并通过试验分析解决实际生产所出现的技术问题,由此形成一套适应于大批量封装生产的IGBT封装工艺技术,成功地应用于分立IGBT器件的批量生产,保证了产品的可靠性,取得了很好的生产效益。     

四自由度集成芯片装片装置

介绍了一种自主研发的四自由度集成芯片装片装置的结构及其基于伺服运动卡控制系统。该装置能在X-Y-Z-θ四个自由度上进行检测和定位，实现芯片与引线框架的待贴片位置的实时对准和绑定，从而保证了较高的装片精度和装片效率。应用结果表明：该装置性能可靠、运行稳定，满足高速度、高精度和高性能先进封装规模化生产线要求。     

低功耗CMOS视觉传感器新结构及其SOC实现

提出了一种新型单片CMOS摄像传感器电路的体系结构,该结构集成了摄像、噪声消除、模数转换、图像处理、图像增强、色彩空间转变等功能.采用该结构实现的CMOS视觉芯片动态范围大,在弱光和强光下均能拍摄图像;工作在30帧的情况下,消耗的功耗只有75 mW,具有低功耗的优点.基于该单芯片低功耗CMOS视觉传感器芯片开发的系统元器件少,可广泛应用于手机拍照、数码相机和网络视频等多媒体终端.     

封装过程中装片后烘烤机理及改善方法探讨

本文探讨并验证了IC封装工序装片后烘烤过程的机理,结合烘烤后失重曲线的分析,重新设计了烘烤升温曲线（烘烤固化）、氮气保护（防止铜材氧化）、抽风（排出挥发物）等工艺参数。验证结果表明,重新设计后的烘烤过程,克服了装片胶挥发污染、铜材氧化这两个对产品可靠性影响最关键的不利因素,降低了装片烘烤工艺对产品可靠性的影响。     

IC封装中引起芯片裂纹的主要因素

芯片裂纹是半导体集成电路封装过程中最严重的缺陷之一。由于芯片裂纹最初发生在芯片的背面,而且有时要在高倍显微镜下才能观察到,所以这种缺陷在很多情况下不易被发现。文章主要介绍和探讨了IC封装过程中引起芯片裂纹的主要原因。划片刀速度、装片顶针位置／顶针高度和吸嘴压力、塑封框架不到位以及切筋打弯异常等都会引起芯片裂纹,从而在从IC焊接到PCB板或使用过程中出现严重的失效和可靠性质量问题。只有了解了导致芯片裂纹的各种因素,半导体集成电路封装厂商才能采取针对性的预防措施杜绝芯片裂纹这种致命的缺陷。     

层叠微芯片封装翘曲行为优化分析

本文以某汽车用芯片为研究对象,研究芯片封装过程结构翘曲优化问题。首先采用Taguchi正交实验设计,结合M oldflow 2016微芯片封装模拟软件,分析各因素对芯片封装过程结构翘曲影响程度及影响规律。选择对芯片翘曲影响较大的因素为响应试验因素,芯片翘曲值为响应目标,进行Box-Behnken试验设计,建立响应面试验因素与目标的数学模型。利用Box-Behnken试验设计构建的数学模型,定义遗传算法优化适应度函数,基于Matlab 2016软件遗传算法工具箱(GUI),通过迭代寻优,获得芯片封装结构翘曲的最小值及最小值时的参数组合。按照芯片翘曲最小值,对芯片原始模型进行反变形补偿,通过实际生产验证,该优化方法具有较高的精度。     

应用于微小卫星的CMOS图像传感器芯片设计

针对小卫星以至微纳卫星领域的应用需求,文章对具有抗辐照能力的CMOS图像传感器的芯片架构和关键技术进行了研究,着重对行列选电路、低噪声信号读出、可编程增益放大器和片上ADC等电路设计技术进行了分析和仿真验证.基于0.35 μm CMOS抗辐照技术和工艺开展了芯片的关键电路仿真、设计和整体版图设计验证.流片后的测试结果表明,该CMOS图像传感器具有高动态、低噪声和抗辐照特点,其噪声电子为42 e-,动态范围为69 dB,当辐射总剂量大于100 krad(Si)时,器件噪声指标符合预期.     

一种基于板壳理论对芯片翘曲变形的研究

在温度变化过程中,由于芯片封装层叠结构及材料热膨胀系数的不匹配,封装结构会发生翘曲现象。芯片翘曲关乎到电子元器件的可靠性及质量,准确快速地计算翘曲对于封装结构设计及材料选型有着重要意义。基于多层板翘曲理论,建立了一套对芯片翘曲进行计算的双曲率模型。以常规的指纹识别芯片为例,通过实验测量及有限元仿真的对比验证,证明了该理论可以满足工程计算精度。该模型可以拓展到其余多层板结构的翘曲计算,对于优化芯片翘曲设计有重要意义。     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Drude-Lorentz色散模型研究光学Tamm态的性质

废旧塑封芯片的界面分层会严重影响其回收重用价值, 一直是废弃电器电子产品(WEEE)资源化研究中关注的热点问题。基于有限元仿真方法, 分析了废旧QFP塑封芯片在线路板拆解温度下的翘曲变形和各材料界面应力分布。研究表明, 拆解温度过高时, 芯片翘曲过大容易导致材料膨胀力失配, 造成界面分层; 在粘结层、衬底和模塑料的结合区域应力水平非常高, 较易发生分层; 模塑料在拆解温度下为玻璃态, 与管芯及衬底的结合强度均降低, 其界面角点均为较易发生分层的位置。     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

Warpage in plastic packages: effects of process conditions, geometry and materials

The effects of several important parameters, including processing conditions, package geometry and materials, are specifically studied on the occurrence of warpage and coplanarity for a plastic package. Special emphasis is placed on the evaluation of moulding compound properties and optimal processing conditions that can effectively minimize warpage. It is found that moulding compounds requiring a low moulding temperature and having a low coefficient of thermal expansion (CTE) can significantly reduce warpage. The elastic modulus was found to be inversely proportional to warpage, indicating the modulus should be kept as high as possible. The post-mould curing is essential to reducing warpage as it increases the glass transition temperature, but lowers the thermal shrinkage. A cross-shaped die paddle against a full square paddle, a thick die attach and a large die size are also favorable to reducing warpage.     

LQFP和eLQFP热机械可靠性的有限元分析

封装形式的差异性对产品可靠性具有重要影响。基于有限元法,对比分析了薄型四方扁平封装(LQFP)和载体外露薄型四方扁平封装(eLQFP)在室温和回流焊温度下的翘曲、芯片和粘片胶的应力水平以及各材料界面应力分布。研究表明,LQFP的翘曲比eLQFP的大,但芯片和粘片胶上的最大应力无明显差别;eLQFP在塑封材料与芯片有源面界面的应力水平比LQFP的大;eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剪切应力比LQFP的大,但eLQFP在芯片与粘片胶界面、粘片胶与芯片载体界面的剥离应力比LQFP的小;eLQFP在塑封材料与芯片载体镀银区界面的应力水平高于LQFP的应力水平,由于塑封材料与镀银芯片载体的结合强度弱,eLQFP更易发生界面分层。     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

B-Spline X-Ray Diffraction Imaging — Rapid non-destructive measurement of die warpage in ball grid array packages

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging (www.itrs.net [1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die.This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 μrad ≈ 0.003° in times as short as 9–180 s (worst case X–Y spatial resolution = 100 μm) for a full 8.7 mm × 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.     

Die-attachment solutions for SiC power devices

Silicon carbide has become a very attractive material for high temperature and high power electronics applications due to its physical properties, which are different than those of conventional Si semiconductors. However, the reliability of SiC devices is limited by assembly processes comprising die attachment and interconnections technology as well as the stability of ohmic contacts at high temperatures.The investigations of die to substrate connection methods which can fulfill high temperature and high power requirements are the main focuses of the paper. This work focuses on die attach technologies: solder bonding by means of gold-germanium alloys, adhesive bonding with the use of organic and inorganic conductive compositions, as well as die bonding with the use of low temperature sintering with silver nanoparticles. The applied bonding technologies are described and obtained results are presented. Of the methods tested, the best solutions for high temperature application are two die attach technologies: silver glass die attach and die bonding with the use of low temperature sintered Ag nanopowders.     

Novel process warpage modeling of matrix stacked-die BGA

A comprehensive warpage analysis is performed on the matrix stacked-die ball grid array BGA (SDBGA) by means of finite-element modeling and experimental warpage measurements. By comparing the block warpage results from conventional linear small deformation simulation and the experimental measurement results, it is found that the linear method is not able to capture the warpage behavior of the SDBGA matrix, because the change of the centroidal moment of inertia of cross section after deformation cannot be considered due to small deformation assumption. The nonlinear large deformation analysis must be taken instead. Based on the nonlinear analysis, an advanced warpage prediction methodology for matrix SDBGA is established. This methodology is then used to characterize the warpage behavior of matrix SDBGA and to study the different effects on the warpage. Warpage of matrix SDBGA during the whole assembly processes is also predicted. For the SDBGA matrix investigated, the crossbow dominant warpage and buckling phenomena are observed for the matrix after bottom die bonding and after interposer bonding, which are new findings in the warpage study for electronic packages. It is also found that not only the total die length, but also the dice distribution will affect the warpage pattern of the matrix. For the matrix after top die bonding and after molding, normal warpage patterns are observed, i.e., both crossbow and coilset warpage are comparable. "Bending interaction" and the "warpage competition" mechanisms are proposed to explain the warpage characteristic for matrix SDBGA.     

HgCdTe焦平面红外探测器封装中的芯片粘接技术

针对HgCdTe焦平面红外探测器封装的特殊性,提出了芯片粘接胶的选用原则,影响粘接质量的主要因素,以及粘接工艺优化方法。提出了用于封装HgCdTe MW 320×256探测器的低温胶X1,并对该胶做了一系列可靠性实验。实验证明,低温胶X1满足该探测器的封装要求。