共查询到18条相似文献,搜索用时 156 毫秒
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埋入堆叠芯片技术在实现封装小型化的同时,增加了封装电学设计的复杂性。以一个数字系统为例,详细阐述了埋入堆叠芯片封装结构的电学设计过程。利用电磁仿真软件提取了该封装结构的寄生参数,并通过S参数、延时、反射分析,确定长绑定线为影响链路信号质量的关键因素,其影响直接限制了埋入堆叠芯片技术的应用范围。运用RLC传输线模型分析了长绑定线造成大的信号质量衰减的原因。最后,提出了一种大幅减短绑定线长度并提升链路电学性能的优化结构,拓展了此技术在高速领域的应用。眼图的对比结构表明,新结构能降低链路的阻抗失配,减小信号延时,并大大改善高速信号的质量。 相似文献
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采用湿度敏感度评价试验及湿-热仿真方法,分析了温湿度对于QFN封装分层失效的影响.通过C-SAM和SEM等观察发现,QFN存在多种分层形式,分层大多发生在封装内部材料的界面上,包括封装塑封材料和芯片之间的界面、塑封材料和框架之间的界面等.此外,在封装断面研磨的SEM图像上发现芯片粘结剂内部有空洞出现.利用有限元数值模拟的方法,对QFN封装的内部湿气扩散、回流过程中的热应力分布等进行了模拟,分析QFN分层失效的形成原因.结果表明,由于塑封器件材料、芯片、框架间CTE失配,器件在高温状态湿气扩散形成高气压条件下易产生分层.最后提出了改善QFN分层失效的措施. 相似文献
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叠层CSP封装工艺仿真中的有限元应力分析 总被引:1,自引:0,他引:1
叠层CSP封装已日益成为实现高密度、三维封装的重要方法。在叠层CSP封装工艺中,封装体将承受多次热载荷。因此,如果封装材料之间的热错配过大,在芯片封装完成之前,热应力就会引起芯片开裂和分层。详细地研究了一种典型四层芯片叠层CSP封装产品的封装工艺流程对芯片开裂和分层问题的影响。采用有限元的方法分别分析了含有高温过程的主要封装工艺中产生的热应力对芯片开裂和分层问题的影响,这些封装工艺主要包括第一层芯片粘和剂固化、第二、三、四层芯片粘和剂固化和后成模固化。在模拟计算中发现:(1)比较三步工艺固化工艺对叠层CSP封装可靠性的影响,第二步固化工艺是最可能发生失效危险的;(2)经过第一、二步固化工艺,封装体中发现了明显的应力分布特点,而在第三步固化工艺中则不明显。 相似文献
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当环境温度、湿度发生变化时,塑料封装集成电路内部的不同物质界面会产生分层,分层导致电路回路的开路或间歇性接触不良,极大地影响IC的功能和使用寿命。封装主要材料BOM(如芯片/框架/装片胶/塑封料环氧树脂)是确定IC MSL等级和分层水平的基础,封装制程的工艺设计、组装过程的控制方法、产品防范外力破坏及热电应力防护都是影响分层的因素,BOM组合需要考虑加强材料间的粘结强度及接近的热膨胀系数、设计芯片PO层减少电路表面凹凸落差、框架沟槽凸台设计、制造过程防污染/防氧化控制等,都是改善IC产品内部分层的有效思路。DOE对比试验有助于从复杂的产品制造过程中发现分层产生的根源。 相似文献
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在高密度小尺寸的系统级封装(SiP)中,对供电系统的完整性要求越来越高,多芯片共用一个电源网路所产生的电压抖动除了会影响到芯片的正常工作,还会通过供电网路干扰到临近电路和其他敏感电路,导致芯片误动作,以及信号完整性和其他电磁干扰问题.这种电压抖动所占频带相当宽,几百MHz到几个GHz的中频电源噪声普通方法很难去除.结合埋入式电容和电源分割方法的特点,提出一种新型高性能埋入式电源低通滤波结构直接替代电源/地平面.研究表明,在0.65~4GHz的频带内隔离深度可达-40~75 dB,电源阻抗均在0.25ohm以下,实现了宽频高隔离度的高性能滤波作用.分别用电磁场和广义传输线两种仿真器模拟,高频等效电路模型分析这种低通滤波器的工作原理以及结构对隔离性能的影响,并进行了实验验证. 相似文献
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芯片叠层封装能够大幅提高集成度,硅通孔技术是集成电路三维封装的发展方向.但是随着封装密度增加功率密度增大,对散热的要求也愈加迫切.对芯片散热的最新进展进行了介绍,着重研究了微管液体冷却技术,在讨论了相关模型的基础上,对微管的制备方法进行了分析. 相似文献
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随着半导体大功率器件的发展,芯片的散热一直是制约功率器件发展的因素之一。而器件内部散热主要是通过芯片背面向外传导,芯片焊接工艺是直接影响器件散热好坏的关键因素之一,合金焊料的一个显著优点就是其导热性能好,因此在散热要求高的大功率器件中使用较为广泛(如Au80Sn20、Au99.4Sb0.6等),但由于合金焊料烧结后会产生较大的残余应力,在尺寸大于8 mm×8 mm的芯片上,烧结工艺应用较少。文章针对11.5 mm×11.5 mm超大面积芯片进行金锡合金烧结试验,经过对应力产生的原因进行分析,从材料、封装工艺等方面采取措施来降低缓释应力,并对封装产品进行可靠性考核验证。试验结果表明,没有芯片存在裂纹、碎裂现象,产品通过了可靠性验证。 相似文献
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《Components and Packaging Technologies, IEEE Transactions on》2006,29(3):551-559
Anisotropic conductive adhesive films (ACFs) have been used for electronic assemblies such as the connection between a liquid crystal display panel and a flexible printed circuit board. ACF interconnection is expected to be a key technology for flip chip packaging, system-in-packaging, and chip size packaging. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. Moisture concentration after moisture absorption was obtained by the finite element method. Then, the vapor pressure in the flip chip during solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. It is found that the delamination is well predicted by the present methodology. 相似文献
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Palaniappan P. Baldwin D.F. Selman P.J. Jaili Wu Wong C.P. 《Electronics Packaging Manufacturing, IEEE Transactions on》1999,22(1):53-62
Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing 相似文献
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Using low-k/ultralow-k (LK/ULK) materials as the inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials are fragile and the mechanical failures in ULK materials are critical during chip packaging processes, such as the solder reflow in the flip-chip. A crack or delamination that initiates within the high thermo-mechanical stress regions can propagate into the active area of the chip in packaging, which involves the chip-packaging interaction (CPI) problem. In this study, we proposed a three-dimensional sub-modeling finite element approach considering an effective layer for the back end of line (BEOL) microstructures in the global model to improve the accuracy. The approach surmounted the difficulty of the large size difference between the chip and the ULK layers in computations. The stress analysis and parametric studies for a designed ULK chip with 40 nm technical node under the flip-chip reflow was performed based on the present method. The effects of the selected parameters were ranked and the optimal combination of the factors was achieved. 相似文献
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Tran S.K. Questad D.L. Sammakia B.G. 《Components and Packaging Technologies, IEEE Transactions on》1999,22(4):519-524
Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses 相似文献
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Shu-Ming Chang Chih-Yuan Cheng Li-Cheng Shen Kuo-Ning Chiang Yu-Jiau Hwang Yu-Fang Chen Cheng-Ta Ko Kuo-Chyuan Chen 《Advanced Packaging, IEEE Transactions on》2007,30(3):377-383
Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing. 相似文献
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W. D. van Driel C. J. Liu G. Q. Zhang J. H. J. Janssen R. B. R. van Silfhout M. A. J. van Gils L. J. Ernst 《Microelectronics Reliability》2004,44(12):406-2027
Interfacial delamination is an often-observed failure mode in multi-layered IC packaging structures, which will not only influence the yield of wafer processes, but also have direct impact on the packaging reliability. The difference in coefficient of thermal expansion, together with thermal and thermal–mechanical loading are the main driving forces for interfacial delamination. First of all, this type of delamination is considered as a mixed mode of failure at the material interfaces. Hence, at least two stress components are needed to predict its occurrence. However, due to the singular stress field at the interface, one could hardly obtain the correct stresses at the interface. Therefore, a combined experimental–numerical method is used to investigate the initiation and propagation of the interface delamination. The purpose of the experimental shear and tensile tests is to measure the critical loads, at which delamination initiates. Then, a Finite Element (FE) model is constructed to convert the critical load into critical failure data for further numerical investigation. The FE model is so constructed that it reproduces the geometrical configurations of the tests. Due to the singular stress distribution at the interface, the calculated local stresses will be both mesh and residual-stiffness dependent. The influences of the FE parameters on the interface stresses are studied. After that, a progressive failure approach is, in combination with a group of failure criteria and the estimated local critical stresses, applied to predict the initiation and propagation of the delamination between epoxy mould compound and the passivation layer in the Integrated Circuit (IC) for three different package structures. The present method and the obtained results are valuable to determine design rules for IC packaging structures. 相似文献