CDMA2000数字中频的设计

在CDMA2000系统中，信道是经过QPSK四相扩频正交调制传输的，数字中频与模拟中频相比能产生严格的幅相平衡正交信号，处理时能保证有严格的线性相位，为此介绍了CDMA2000系统数字中频调制解调实现的方案，对其中抗混叠滤波器，数字频率合成器的设计方法进行了详细的讨论，最后给出了用基于高密度逻辑门电路可编程集成片编辑器（FPGA Compiler)实现的结果。     

On Bounds of Shift Variance in Two-Channel Multirate Filter Banks

Critically sampled multirate FIR filter banks exhibit periodically shift variant behavior caused by nonideal antialiasing filtering in the decimation stage. We assess their shift variance quantitatively by analysing changes in the output signal when the filter bank operator and shift operator are interchanged. We express these changes by a so-called commutator. We then derive a sharp upper bound for shift variance via the operator norm of the commutator, which is independent of the input signal. Its core is an eigensystem analysis carried out within a frequency domain formulation of the commutator, leading to a matrix norm which depends on frequency. This bound can be regarded as a worst case instance holding for all input signals. For two channel FIR filter banks with perfect reconstruction (PR), we show that the bound is predominantly determined by the structure of the filter bank rather than by the type of filters used. Moreover, the framework allows to identify the signals for which the upper bound is almost reached as so-called near maximizers of the frequency-dependent matrix norm. For unitary PR filter banks, these near maximizers are shown to be narrow-band signals. To complement this worst-case bound, we derive an additional bound on shift variance for input signals with given amplitude spectra, where we use wide-band model spectra instead of narrow-band signals. Like the operator norm, this additional bound is based on the above frequency-dependent matrix norm. We provide results for various critically sampled two-channel filter banks, such as quadrature mirror filters, PR conjugated quadrature filters, wavelets, and biorthogonal filters banks.     

Linear periodic systems and multirate filter design

We present a systematic procedure for the design of filters intended for multirate systems. This procedure Is motivated by viewing the equiripple design of filters in linear time-invariant systems as a process of obtaining optimum minimax filters for a class of bounded energy input signals. The philosophy of designing optimum minimax filters for classes of input signals is extended to multirate systems, which are not time-invariant. We develop a generalized Fourier analysis appropriate for linear periodic systems and use it to derive new error criteria for multirate filter design. Using such criteria yields optimum minimax multirate filters for the input signal class. The utility of our method is demonstrated by using it to analyze several multirate systems. We give numerical results on the design of a multirate implementation of a narrowband filter and compare our work to previous work on multirate filter design. Our numerical analysis is based upon a new formulation of the design as a semi-infinite linear programming problem     

Optimal signal reconstruction in noisy filter bank systems:multirate Kalman synthesis filtering approach

A multirate Kalman synthesis filter is proposed in this paper to replace the conventional synthesis filters in a noisy filter bank system to achieve optimal reconstruction of the input signal. Based on an equivalent block representation of subband signals, a state-space model is introduced for an M-band filter bank system with subband noises. The composite effect of the input signal, analysis filter bank, decimators, and interpolators is represented by a multirate state-space model. The input signal is embedded in the state vector, and the corrupting noises in subband paths are generally considered as additive noises. Hence, the signal reconstruction problem in the M-band filter bank systems with subband noises becomes a state estimation procedure in the resultant multirate state-space model. The multirate Kalman filtering algorithm is then derived according to the multirate state-space model to achieve optimal signal reconstruction in noisy filter bank systems. Based on the optimal state estimation theory, the proposed multirate Kalman synthesis filter provides the minimum-variance reconstruction of the input signal. Two numerical examples are also included. The simulation results indicate that the performance improvement of signal reconstruction in noisy filter bank systems is remarkable     

Implementation of a tracking Kalman filter on a digital signalprocessor

A Kalman filter for tracking moving objects has been implemented on a TMS32010 digital signal processor. Tracking accuracy and quantization effects of the implementation have been measured by comparing the filter to one implemented on a general-purpose computer with a 32 bit word length. The filter design has been optimized to minimize the program memory requirements and execution speed. Although the filter has been implemented on a specific signal processing chip, the design is general enough to be applicable to any other digital signal processor. The filter can be used for tracking objects for industrial or other applications where range and bearing measurements are available. For motion on a plane, the filter can be used to track objects where the maximum system bandwidth is 1680 Hz; for three-dimensional motion the system bandwidth is 1120 Hz. Using the approach presented, higher system bandwidth can be accommodated through higher-speed digital signal processors     

Design and implementation of a low-pass filter for microsensor signal processing

A novel low-pass filter that consists of a switched capacitor filter(SCF) and its antialiasing prefilter and smoothing postfilter is proposed for a microsensor signal processing system,which is used in separation point detection on the surface of micro air vehicles.In the system,the filter is not only applied to finish the function of filtering but also used as the front end antialiasing filter of the over sampling analog-to-digital converter.This proposed implementation mostly relies on the design of a ...     

Optimized interpolator filters for timing error correction in DMTsystems for xDSL applications

Discrete multitone (DMT) modulation is a multicarrier technique that allows the transmission of high speed data over band limited channels. This type of system is very sensitive to synchronization errors when used in digital subscriber loop applications (xDSL), due to the high number of carriers and high density constellations involved. This paper addresses the topic of all-digital timing error correction in a DMT system for xDSL applications, where the timing error correction procedure is based entirely on signal interpolation. An analytical study of the interpolator filter performance is carried out, arriving at an expression for the signal-to-distortion ratio (SDR) at the output of the receiver, as a merit figure. In this derivation, the fixed frequency domain equalizer (FEQ) plays an important role since it compensates for a great part of the distortion introduced by the interpolator. From this study, the design of the optimal interpolator filter in terms of SDR, based on a multirate approach with Kaiser window, is presented. Specific designs for ASIC and for DSP-based implementations are obtained. Performance results are excellent, yielding SDR values above 50 dB for all carriers while keeping the computational cost low     

Implementation of a Multirate Speech Digitizer

In this paper, implementation of a compact and efficient multirate speech digitizer with variable transmission rates of 2.4, 4.8, 9.6, and 14.96 kbits/s is presented. The multirate algorithm has been made based on the residual-excited linear prediction (RELP) vocoder with a transmission rate of 9.6 kbits/s. The residual encoder employed in the RELP vocoder uses hybrid companding delta modulation (HCDM). This HCDM is also used as a 14.96 kbit/s coder. If the residual in the RELP system is down-sampled before encoding, a 4.8 kbit/s coder can be realized. If the residual encoder is not used, a 2.4 kbit/s linear predictive coder (LPC) can be realized by incorporating a pitch extractor. In the 4.8 and 9.6 kbit/s coders the pitch-implanted residual excitation method has been used to generate the excitation signal to the synthesis filter. The multirate speech digitizer algorithm has been implemented using 2900 series bit-slice microprocessors. The external memory is composed of 2K RAM's and 2K ROM's. The system design is a two-bus structure with a 204 ns cycle time. With efficient hardware and software design, the multirate speech digitizer requires almost the same hardware complexity as compared with the conventional 2.4 kblt/s LPC vocoder.     

A Generic Open-Loop Algorithm for Three-Phase Grid Voltage/Current Synchronization With Particular Reference to Phase, Frequency, and Amplitude Estimation

This paper presents a new open-loop architecture for three-phase grid synchronization based on moving average and predictive filters, where accurate measurements of phase, frequency, and amplitude are carried out in real time. Previous works establish that the fundamental positive sequence vector of a set of utility voltage/current vectors can be decoupled using Park's transformation and low-pass filters. However, the filtering process introduces delays that impair the system performance. More specifically, when the input signal frequency is shifted above the nominal, a nonzero average steady-state phase error appears in the measurements. To overcome such limitations, a suitable combination of predictive and moving average finite impulse response (FIR) filters is used by the authors to achieve a robust synchronization system for all input frequencies. Moving average filters are linear phase FIR filters that have a constant time delay at low frequencies, a characteristic that is exploited to good effect to design a predictive filter that compensates such time delays, enabling zero steady-state phase errors for shifted input frequencies. In summary, the main attributes of the new system are its good frequency adaptation, good filtering/transient response tradeoff, and the fact that its dynamics is independent of the input vector amplitude. Comprehensive experimental results validate the theoretical approach and the high performance of the proposed synchronization algorithm.      

分数阶傅里叶域两通道滤波器组

 基于两通道滤波器组构建的子带信号处理方法已在图像、语音信号处理中得到广泛的应用.本文从分数阶傅里叶域多抽样率信号处理基本理论和分数阶卷积定理出发,推导了分数阶傅里叶域两通道滤波器组准确重建的基本条件,并基于传统傅里叶域有限长标准正交镜像滤波器组和共轭正交镜像滤波器组的原型滤波器设计了分数阶傅里叶域标准正交镜像滤波器组和共轭正交镜像滤波器组.本文所提出的结论为分数阶傅里叶域滤波器组理论的建立提供了基本依据,同时也为分数阶傅里叶变换在图像、语音信号处理等工程实践中的应用奠定了理论基础.最后,仿真实验验证了所提分数阶傅里叶域滤波器设计方法的有效性.     

利用插值法提高采样率的滤波器设计

随着数字信号的迅速发展,在现代数字系统中对超过单一采样率的处理已经越来越普遍,这直接导致了多采样率处理作为数字信号处理(DSP)中一个新的分支领域的出现。其中在进行D/A(数字/模拟)转换的场合,往往需要提高数字信号采样率来降低对模拟滤波器的要求。论述利用插值的方法来提高采样速率,介绍了内插原理和给出了一种多相滤波器的设计方法,使性能和资源占有率得到较大的突破,最大限度地减少资源消耗。     

基于自适应Kalman滤波的二维有噪子带信号恢复

基于子带信号的多通道表示（multichannel representation)和输入信号的动态特征,本文尝试推出了一种多分辨率状态空间模型,它与带相加子带噪声的滤波器组（Filter Bank)系统是等价的,于是使有噪子带信号的恢复可表述为相应多分辨率态空间模型的最优状态估计问题。进一步又利用信号的向量动态模型,发展了适于二维Kalman滤波的二维多分辨率状态空间模型,根据信号行为的分布,目标平面（object plane)可分割为不同的区域并用不同的向量动态模型来表征信号的非平衡分布,计算机数字仿真结果进一步证实了本文所提出了二维多分辨率Kalman滤波器性能的优越性。     

通用载波同步模块的设计与实现

通信系统能否有效、可靠地工作,很大程度上依赖于有无良好的载波同步模块。阐述了某通用解调器中载波同步模块的设计与实现,主要由相位旋转器、鉴相器、环路滤波器、NCO（数字振荡器）等组成,可适用于MPSK（多进制相移键控）、MQAM（多进制正交幅度调制）等多种调制信号。然后针对特定的环路滤波器参数进行了计算机仿真,并给出了相应的FPGA（现场可编程门阵列）设计与硬件实现结果。     

适用于短码捕获的匹配滤波器的实现结构

扩频码（伪随机码,PN码）捕获是扩频通信中扩频码同步的一个重要环节,基于匹配滤波器的捕获方法具有捕获时间短的优势,比较适合短码的捕获和实时通信的场合。为解决数字匹配滤波器资源占用多的问题,根据扩频码取值的双极性特性,针对数据过采样的应用场合,提出了一种基于FPGA实现的数字匹配滤波器的结构。该结构为两级滤波器形式,无乘...     

用于改变图像大小的M带插值滤波器设计

改变图像尺寸是多速率系统的重要应用之一。提出了一种通过采样率转换改变图像尺寸的有效方法，给出了线性相位FIR插值滤波器和线性相位FIR抗混叠滤波器的设计算法。结合实例说明了方法的有效性。     

QPSK全数字接收机定时同步环路

将三阶立方拉格朗日多项式内插算法和Gardner定时误差检测算法应用于QPSK全数字接收机定时同步环路,并对构成环路的其他部分,环路滤波器以及数控振荡器进行分析并提出实现方法。通过仿真,证明上述算法具有良好的性能,可以很好的解决定时同步问题,并在FPGA上实现整个环路设计方案,使得数字解调的硬件实现具有良好的灵活性和可移植性。     

A Linear Prediction Based Estimation of Signal‐to‐Noise Ratio in AWGN Channel

Most signal‐to‐noise ratio (SNR) estimation techniques in digital communication channels derive the SNR estimates solely from samples of the received signal after the matched filter. They are based on symbol SNR and assume perfect synchronization and intersymbol interference (ISI)‐free symbols. In severe channel distortion where ISI is significant, the performance of these estimators badly deteriorates. We propose an SNR estimator which can operate on data samples collected at the front‐end of a receiver or at the input to the decision device. This will relax the restrictions over channel distortions and help extend the application of SNR estimators beyond system monitoring. The proposed estimator uses the characteristics of the second order moments of the additive white Gaussian noise digital communication channel and a linear predictor based on the modified‐covariance algorithm in estimating the SNR value. The performance of the proposed technique is investigated and compared with other in‐service SNR estimators in digital communication channels. The simulated performance is also compared to the Cramér‐Rao bound as derived at the input of the decision circuit.     

一种新的多频连续波雷达数据采集系统设计

给出了一种基于多速率信号处理的多频连续波雷达数据采集系统设计和实现方法。分析了抽取的时域和频域特性,针对多频连续波雷达的应用背景,分析了实际系统中抽取比的选择,设计了合适的抗混叠滤波器。给出了一种FIR实现信号抽取的高效结构。在此基础上,完成了数据采集系统的硬件设计和软件设计。该方案具有控制灵活,数据传输高速、稳定等特点。该设计已经成功应用于实际系统。     

Design of wideband all-digital phase locked loops using multiratedigital filter banks

All-digital phase locked loops (DPLLs) have many advantages over analog loops. However, due to digital device limitations and costs, superwide PLLs with front-end bandwidths as high as one gigahertz are commonly implemented using analog parts. This article presents a new architecture that allows an all-digital implementation of superwide PLLs. The problem of operating digital components at high speed is avoided here (without reducing the front-end bandwidths) by inserting a multirate digital filter bank in front of the DPLL. The new design is shown to have steady-state and transient performance that is identical to a conventional DPLL     

Design techniques for high-speed multirate multistage FIR digital filters

This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25?µm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714?MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.