Characterization of fritting phenomena on Al electrode for low contact force probe card

We have investigated the characteristics of fritting of thin oxide film on an aluminum electrode for application to a probe card with low contact force. The fritting is a kind of electric breakdown of oxide film on metal electrode. It can be utilized for making electric contacts between the test probe and the electrode on LSI chips without a large force. The voltage and the contact force needed to cause fritting on a sputtered Al film was measured using W, BeCu and Pd needle probes. The contact resistance was also measured. A fritting was occurred by applying a contact load of 1 mN and voltage of 5 V. The contact resistance decreases with increasing the maximum current that passes through the contact. A current of 500 mA is enough to obtain the contact resistance of 1 /spl Omega/, which is low enough in practical test of signal lines. No damages were found on the Al film by optical microscope and scanning electron microscope observation.     

Composite Spreader for Cooling Computer Chip With Non-Uniform Heat Dissipation

The performance of a composite spreader, with a 0.4 mm thick top layer of porous graphite (PG), for enhanced cooling with nucleate boiling of FC-72 dielectric liquid, and a 1.6 mm copper (Cu) substrate, for achieving better cooling of underlying 10 X 10 mm computer chip, with a non-uniform surface heat flux, is investigated. This spreader takes an advantage of the enhanced nucleate boiling heat transfer of FC-72 dielectric liquid on PG and the good heat spreading by Cu. The dissipated thermal power by the chip has a cosine-like distribution with a peak-to-average heat flux, Phi_max, which varied up to 2.467. The spreader surface area, the total thermal power dissipated by the chip, removed from the surface of the spreader, and the total thermal resistance are calculated and compared with those of PG and Cu spreaders of same thickness, 2.0 mm. With Phi_max = 2.467, 39.48 W and 72.0 W can be removed from the surface of composite spreaders cooled with saturation and 30 K subcooled boiling, compared to 43.0 and 65.3 W for Cu spreaders. The calculated surface areas and total thermal resistances of the composite spreaders, 6.82 cm² and 4.90 cm² and 0.284 and 0.68degC/W, are smaller than for Cu spreaders, 12.26 cm² and 11.92 cm², and 0.51 and 0.83degC/W. In addition, the calculated chip maximum surface temperatures of 62.37degC and 72.2degC, are lower than with Cu spreaders (72.67degC and 76.30degC).     

0.25 μm Self-Aligned AlGaN/GaN High Electron Mobility Transistors

Self-aligned AlGaN/GaN high electron mobility transistors grown on semiinsulating SiC substrates with a 0.25 mum gate-length were fabricated using a single-step ohmic process. Our recently developed Mo/Al/Mo/Au-based ohmic contact requiring annealing temperatures between 500degC and 600degC was utilized. Ohmic contact resistances between 0.35-0.6 Omega ldr mm were achieved. These 0.25 mum gate-length devices exhibited drain current density as high as 1.05 A/mm at a gate bias of 0 V and a drain bias of 10 V. A knee voltage of less than 2 V and a peak extrinsic transconductance (g_m ) of 321 mS/mm were measured. For their microwave characteristics, a unity gain cutoff frequency (f_T ) of 82 GHz and maximum frequency of oscillation (f _max) of 103 GHz were measured.     

Pressure Contact Micro-Springs in Small Pitch Flip-Chip Packages

This work investigates electrical pressure contacts based on a micro-spring with orders of magnitude smaller pitch and force than conventional pressure contacts. The springs are beams which curl out of the surface and can be used for wafer-scale testing and packaging. They are fabricated with standard wafer-scale thin film techniques and have been previously demonstrated on active silicon integrated circuits. Single springs and their electrical contacts are characterized with force versus compression and compression versus resistance measurements. Flip-chip packages with hundreds of micro-springs were assembled with 20-mum pad pitch and 40-mum spring pitch. Each spring operates with a force of approximately 0.01 g and contacts a gold pad. These packages are shown to have stable resistance values during both in-situ thermocycle (0degC to 125degC) and humidity testing (60degC at 95%RH). Spring electrical contacts inside the package are shown not to degrade during environmental testing through measurements of four-wire resistance and electrical isolation structures. High-speed glitch measurements are performed to confirm that the pressure contact does not have intermittent opens during thermocycling. These results suggest that a low-force solder-free pressure spring contact is a viable technology for next generation flip-chip packaging     

Thermosonic Flip Chip Interconnection Using Electroplated Copper Column Arrays

A novel flip chip process is reported in which bare dies are thermosonically bonded to arrays of electroplated copper columns formed on a substrate. The new process is intended as a low-cost, lead-free chip-on-board (COB) interconnection method for high-frequency devices. A detailed study has been performed of the electroplating and thermosonic bonding techniques involved. It was found that oxygen plasma treatment of the resist mask could increase the yield of the fine-pitch (<150 mum) column electroplating process, while the flatness of the resulting columns was affected by the plating current density and the sidewall profiles in the resist mold. Under optimal conditions, column arrays with flat tops could be produced with a 100% yield, and with a column height deviation of less than 0.5 mum over an area of 10 mmtimes10 mm. The array thermosonic bonding process was studied with the aid of Box-Behnken design of experiments based on response surface methodology. A second-order relationship between the input bonding variables and the bonding strength was derived and used to determine optimal process conditions. With this optimized process, silicon chips with aluminium metallization were thermosonically flip chip bonded to quartz test boards bumped with gold-capped copper columns. Sixteen prototype assemblies without underfill protection were evaluated by accelerated lifetime tests. The contact resistances of single column connections showed no significant change after 50 thermal shocks of 0 degC to 100 degC, and samples subjected to high-temperature storage remained intact at all bonding interfaces after 1.5 h at 300 degC. Thermal cycling between -55degC and 125 degC produced open-circuit defects in a small number of connections after 70 cycles     

Analysis of RF MEMS switch packaging Process for yield improvement

Radio frequency microelectro-mechanical systems (RF MEMS) switches offer significant performance advantages in high-frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320degC. The assembled packages were then attached to a printed circuit board at 220degC. During the process, some switches failed due to electrical shorting. Interestingly, more failures were observed at the lower temperature of 220degC rather than 320degC. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

A Pyrenylpropyl Phosphonic Acid Surface Modifier for Mitigating the Thermal Resistance of Carbon Nanotube Contacts

Efforts to utilize the high intrinsic thermal conductivity of carbon nanotubes (CNTs) for thermal transport applications, namely for thermal interface materials (TIMs), have been encumbered by the presence of high thermal contact resistances between the CNTs and connecting materials. Here, a pyrenylpropyl‐phosphonic acid surface modifier is synthesized and applied in a straight forward and repeatable approach to reduce the thermal contact resistance between CNTs and metal oxide surfaces. When used to bond nominally vertically aligned multi‐walled CNT forests to Cu oxide surfaces, the modifier facilitates a roughly 9‐fold reduction in the thermal contact resistance over dry contact, enabling CNT‐based TIMs with thermal resistances of 4.6 ± 0.5 mm² K W^?1, comparable to conventional metallic solders. Additional experimental characterization of the modifier suggests that it may be used to reduce the electrical resistance of CNT‐metal oxide contacts by similar orders of magnitude.     

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO₂ layer through thermal desorption spectroscopy measurements.     

TiN-CVD process optimization for integration with Cu-CVD

Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter- and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu/SiO₂ interconnection structures. After a review of the TiN-CVD performance as a diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu/TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/Cu-CVD process integration.     

A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements

To explore the possibility of soft intellectual property implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or system-on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the pulse with a temperature-proportional width. The timing reference is just the input clock and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit was implemented by field-programmable gate array chips for functionality verification and performance evaluation. Realized with as few as 140 logic elements, the proposed smart sensor was measured to have an error of -1.5 ~ 0.8 degC over the full commercial IC temperature operation range of 0 degC-75 degC for thermal self-sensing or monitoring. The effective resolution can be made better than 0.1 degC easily, and the power consumption is 8.42 muW at a sampling rate of 2 samples/s. The longest conversion time is around 260 s, and a conversion rate of 3 kHz at least is promised.     

Adhesion improvement of Cu-based substrate and epoxy molding compound interface by hierarchical structure preparation

For microelectronic industry, Cu-based substrate and epoxy molding compound (EMC) interface is inherently weak and most likely to delaminate, well-known as a major threat for integrated circuits (ICs) reliability. In this paper, hierarchical whisker-like oxide/Cu cone structure was for the first time to be fabricated by combining electroless plating with heat treatment methods to enhance the interface adhesion between Cu-based substrate and EMC. The surface morphology was characterized by scanning electron microscope (SEM). Result shows that the hierarchical whisker-like oxide/Cu cone film is fine, dense and uniform; Single Cu cone structure is about 3–5 μm in height and 1 μm in root diameter; a layer of whisker-like oxide grows perpendicularly to circular surface of Cu cone, with length ranging from tens to hundreds of nanometers. Adhesion strength between the as-prepared substrates and EMC were measured by button shear test. With consideration of oxidation caused by practical processes (e.g. wire bonding), the interface of EMC and porous oxide formed at 260 °C for 5 min was taken as standard sample, representative of practical interface. To further study the effect of whisker-like oxide and Cu cone solely on adhesion performance, whisker-like oxide, porous oxide/Cu cone were investigated as well. Button shear test results reveal that interfacial adhesion strength of EMC and whisker-like oxide, porous oxide/Cu cone, hierarchical whisker-like oxide/Cu cone are 85%, 110% and 162% higher than that of standard interface. Moreover, the mechanism for adhesion improvement was discussed by facture surface observation, failure path assumption and force–displacement curve analysis. Results show that interface of EMC and hierarchical whisker-like oxide/Cu cone exhibits brittle/ductile property with about 3–5 μm thick EMC left on the fracture surface, indicating cohesive failure caused by remarkable mechanical interlocking effect.     

An Investigation of Wafer Probe Needles Mechanical Properties and Contact Resistance Changing Under Multiprobing Process

In the semiconductor industry, fabrication defects in integrated circuit chips are generally identified using a needle probe card. Ideally, the probe needles should have a high elastic modulus and should maintain a low contact resistance even following repeated surface contacts. Using a high-precision microforce tensile tester, this study commences by investigating the thermo-mechanical properties of tungsten (W), tungsten-rhenium (ReW), and beryllium-copper (BeCu) probe needles. The tensile tests are conducted at temperatures ranging from room temperature to 150 degC at a loading rate of approximately 4 mm/min. Stress-strain curves are constructed to examine the temperature dependence of the elastic modulus, yield stress, and fracture strain of each needle. The experimental data are then employed to develop an empirical formula to predict the stress-strain response of the three needles. Subsequently, a single-contact probing test is performed to investigate the effect of the overdrive displacement on the scrub mark length, contact force, and contact resistance for each type of needle. Finally, a multicontact probing test is performed to evaluate the effect on the contact resistance of surface particle accumulation on the probe tip following repeated surface contacts.     

Analysis of Failure Mechanism in Anisotropic Conductive and Non-Conductive Film Interconnections

Failure behaviors of anisotropic conductive film (ACF) and non-conductive film (NCF) interconnects were investigated by measuring the connection resistance. The four-point probe method was used to measure the connection resistance of the adhesive joints constructed with Au bump on Si chip and Cu pad on flexible printed circuit. The interconnection reliability was evaluated by multiple reflow process. The connection resistance of the ACF joints was markedly higher than that of NCF joints, mainly due to the constriction of the current flow and the intrinsic resistance of the conductive particles in ACF joints. The connection resistances of both interconnections decreased with increasing bonding force, and subsequently converged to about 10 and 1 mOmega at a bonding force of 70 and 80 N, for the ACF and NCF joints, respectively. During the reflow process, two different conduction behaviors were observed: increased connection resistance and the termination of Ohmic behavior. The former was due to the decreased contact area caused by z-directional swelling of the adhesives, whereas the latter was caused by either contact opening in the adhesive joints or interface cracking.     

Electromigration Reliability and Morphologies of 62Sn–36Pb–2Ni and 62Sn–36Pb–2Cu Flip-Chip Solder Joints

The near-eutectic Sn-Pb-Cu and Sn-Pb-Ni ternary solder alloys were developed based on the consideration of strength and fatigue reliability enhancement of solder joints in part via the altering of formation of interfacial intermetallic compounds. In this work, we examine electromigration reliability and morphologies of 62Sn-36Pb-2Ni and 62Sn-36Pb-2Cu flip-chip solder joints subjected to two test conditions that combine different average current densities and ambient temperatures: 5 kA/cm² at 150 degC and 20 kA/cm² at 3 degC. Under the test condition of 5 kA/cm² at 150 degC, 62Sn-36Pb-2Cu is overwhelmingly better than 62Sn-36Pb-2Ni in terms of electromigration reliability. However, under the test condition of 20 kA/cm2 at 30 degC, the electromigration fatigue life of 62Sn-36Pb-2Ni shows a profuse enhancement and exceeds that of 62Sn-36Pb-2Cu. Electromigration-induced morphologies are also examined on the cross sections of solder joints using scanning electron microscopy.     

Corrosion inhibition by self-assembled monolayers for enhanced wire bonding on Cu surfaces

Corrosion inhibition by thiol-derived self-assembled monolayers (SAMs) on Cu surfaces has been characterised using contact angle measurements, X-ray photoelectron spectroscopy, voltammetry, and thermal desorption spectroscopy. Factors influencing SAM formation were investigated to develop an optimised wafer level process. XPS confirms the formation of thiolate species bonded to a mixed metallic Cu and cuprous oxide surface. Stability studies as a function of temperature and electrochemical potential demonstrate promising passivation properties. The feasibility of exploiting SAMs in microelectronics applications was demonstrated by the enhancement of Cu wire bonding onto Cu bond pads.     

Silicon cantilever arrays with by-pass metal through-silicon-via (TSV) tips for micromachined IC testing probe cards

In this paper, an integrated probe card is proposed and developed for wafer-level IC testing. Based on micromachining technology, totally about 26,000 cantilever-tip probes can be formed simultaneously in one 4-in. silicon wafer, with the minimum pitch of 35 μm for adjacent probing tips. The probe card is designed with a novel composite structure that combines both single-crystalline silicon and electroplated metals. In the composite structure, a novel bypass through-silicon-via with a low aspect ratio can be high-yield fabricated for transferring the testing signals from the probing sided (at the wafer bottom side) to the I/O interface (at the front side). The probe card makes full use of the advantages of the single-crystal silicon and the electroplated nickel and copper. Bulk micromachined silicon cantilevers behave uniform probing height and a good elastic deformation property, while the electroplated nickel probing tips promise high hardness and satisfactory electric contact performance with the dies-under-test (DUT). Measurements show that the fabricated cantilever is able to withstand a contact force of 80mN by a tip displacement of 20 μm. The measured contact resistances on metal pads (Al, Cu, and Au) are all below 1 Ω, whereas the maximum current leakage is 64 pA for 3.3 V voltage across two adjacent tips. After a probing reliability test of 100,000 cycles, the cantilever-tip shows no sign of any performance degradation.     

表面粘连效应对接触式微开关接触电阻的影响

建立了一个微开关接触电阻模型．模型将粗糙的触头表面理想化为多微丘结构,并考虑了表面粘连效应,给出了接触电阻与接触力之间的变化关系．结果显示,在低接触力下,粘连效应十分重要．粘连模型与Majumder等人所建立的模型以及实验值的比较结果表明,粘连效应可以用来解释弹性模型与实验之间的偏差．     

A novel contact process for power MOSFET's

A novel technique of making electrical contact to the p diffusions of a DMOS power transistor by over-sintering the aluminum/ silicon contact is reported. The potential advantages are the elimination of a critical masking step and smaller cell size. Test devices showed somewhat higher contact resistances to the n and p diffusions than achievable by the conventional process. Good I-V characteristics and yield were obtained over a wide range of contact process conditions.     

Erosion and contact resistance performance of materials for slidingcontacts under arcing

In our previous work, we have investigated copper sliding switching contacts for automotive power applications. In order to improve their reliability, we have studied in this present paper, alternative materials to copper such as silver based materials (Ag, AgSnO₂, AgC, and AgCNi). Their performance was evaluated by measuring mass variations and contact resistance stability during sliding. The contacts are operated in a test machine during 50000 sliding operations, under inductive loads which produce long arcs, or under lamp loads which produce a short arc. In most cases, we have seen a significant wear of the anode compared to the cathode. We believe that the wear process for the sliding contact is the abrasion of the track by a rough contact surface. This roughness is produced and renewed by material transfer because of arcing. Regarding this wear, we show the medium performance of Ag and Cu contacts, while the worst performance is obtained with AgC and AgCNi, which make these latter materials unsuitable. Regarding contact resistance, we have measured low values <1 mΩ for AgC, AgCNi, and Ag. With AgSnO₂ and Cu contacts, the resistance ran reach high values, especially with an inductive load, which make these latter materials unsuitable. Concerning the effect of operating parameters, we show that polarity may emphasize the already poor performance of a high wear anode by disturbing the sliding motion. In addition, contact force and shape size are found to act on material performance: low force and large shape (cylinder) reduce wear and enhance resistance whereas high force and small shape increases wear and lowers contact resistance