An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 muW (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.     

A Function Generator for Neurophysiological Applications

A function generator is described that basically generates a trapezoidal waveform whose leading and trailing ramps and positive and negative plateaus can be varied in duration, independently, between 0.5 ms and 50 s. By appropriate interconnections between the constituent units of the generator, a total of 12 different waveforms are generated, including triangular, sinusoidal, square, rectangular, and sawtooth waveforms. The output may be either free running or externally triggered to produce an adjustable integral number of cycles.     

一种数字控制可调增益放大器

介绍了一种基于R-2R梯形电阻网络原理的CMOS数字控制可调增益放大器,放大器的增益由数字信号控制线性调节,增益调节的步长可根据不同需要调整变换,进行高精度的线性增益调节。     

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.     

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

A novel transmitter for ultra-wideband (UWB) impulse radio has been developed. The proposed architecture enables low-power operation, simple design, and accurate pulse-shape generation. The phase and amplitude of the pulse are controlled separately and digitally to generate a desired pulse shape. This digital control method also contributes to the low-power transmission and eliminates the need for a filter. The transmitter is fabricated using a 0.18-mum CMOS process. The core chip size is only 0.40 mm². From experimental measurements, it was found that the generated signal satisfied the FCC spectrum mask, and the average power dissipation was only 29.7 mW at A 2.2-V supply voltage. Therefore, the developed UWB transmitter generates accurate pulses with low power consumption and simple design architecture     

A Microprocessor-Based Synchronization Scheme for Digitally Controlled Three-Phase Thyristor Power Converters

This paper presents a microprocessor-based scheme that generates the necessary synchronization logical signals for three-phase static power converter control systems. The problem of detecting the phase-to-phase voltage zero-crossing in presence of noise generated by thyristor commutations in constant and in variable frequency supplies is discussed, and a microcomputer software solution is proposed.     

高精度宽带数字控制可变增益放大器的设计

设计了一种高精度宽带数字控制可变增益放大器,利用增益加强技术改进可变增益放大器的步进精度;同时,引入零点抵消技术,并加入源极负反馈电容,在不增加额外功耗的条件下,拓展了带宽。该电路采用0.18μm CMOS工艺,1.8V供电电源,增益动态范围为62dB,步进精度为1dB,步进误差为0.2dB。设计的可变增益放大器可以提供高达80MHz的带宽,整个电路消耗1.5mA电流,芯片尺寸为300μm×800μm。     

A Feedback Controlled Stimulator That Delivers Controlled Displacements or Forces to Cutaneous Mechanoreceptors

Based on a design by the root locus method and utilizing both displacement and force feedback an instrument is described which can be used to deliver either controlled displacement or controlled force stimuli to the skin. Examples of the stimulator operated in each of its two modes are given.     

基于数字控制方式的DC-DC转换器系统设计

文章给出了应用于高频数字控制DC—DC系统设计的两种方法。基于功率级的S域平均模型,采用传统的Redesign方法,得到数字PID控制的系统离散模型。针对数字PID控制的DC-DC系统的负载调节能力,提出了一种采用Direct—Digital方法实现的三阶数字控制器。基于Matlab／Simulink的系统仿真结果表明,当负载电流在500mA到1A跳变时,提出的三阶补偿系统的最大过;中电压160mV,稳定时间为30μs,相比二阶PID补偿系统竹过冲为450mV,稳定时间为110μs,负载调节性能得到很大的改善;同时,当输入电压在1μs内从3V跳变到5V时,三阶补偿系统的过;中电压和稳定时间分别为450mV和45μs,相比二阶补偿系统的过冲为610mV,稳定时间115μs,线性调节能力也得到较大改善。     

数控高频振荡器的设计

介绍了目前常用的数控延迟单元电路结构,详细分析了这些电路的优缺点.在此基础上,对其中一种电路结构进行了详细的理论分析,改进了电路结构,规范了电路设计的具体步骤,并通过大量的电路模拟,印证了理论分析的正确性.以此延迟单元为核心,在SMIC 0.13μm工艺下,设计实现了一款数控高频振荡器.该振荡器的频率范围高达700 MHz,最高稳定输出频率可达到1 GHz.由于采用全数字实现方式,其功耗最大值不到0.7 mW,版图面积只有26μm×36μm.该电路已成功应用于一个锁相环电路的设计中.     

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.     

System Optimization?Self-Adaptive Controller for Digitally Controlled Thyristor Converters

A self-adaptive controller is described which can automatically adjust the regulatable parameter values in a digital or discrete-data control system to obtain an optimized response with respect to given operating criteria. Problems where system configuration and transfer function are unknown can be handled by a model which emulates the system elements. The controller uses a traditional hill-climbing search procedure effectively implemented in real time by low-cost microprocessor.     

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

A digitally controlled oscillator (DCO) to be used in an all-digital phase-locked loop (PLL) is presented which offers a wide operating frequency range, a monotonic gain curve, and compensation for instantaneous supply voltage variation. The monotonic and wide oscillation frequency is achieved by interpolating at the fine tuning block between two nodes selected from a coarse delay line. Supply voltage compensation is obtained by dynamically adjusting the strength of the feedback latch of the delay cell in response to the change of the supply voltage.      

一种用于IR-UWB的数控环形振荡器设计

设计了一个应用于超宽带脉冲无线电（IR-UWB）通信系统的数控环形振荡器（DCRO）.DCRO采用3调谐,包括电压粗调谐和开关变容管精调谐,逐级提高调谐精度.提出了一种新型延时单元,采用多环路结构,提高了环形振荡器的振荡频率,降低了功耗.设计采用CSMC 0.18μm互补金属氧化物半导体工艺,电源电压1.8V,使用SpectreRF仿真验证,数控环形振荡器的调谐范围为3～8.6GHz,调谐精度为2MHz,当工作频率在8.6GHz时,偏离主频10MHz处相位噪声为-112.4dBc/Hz,功耗为20mW.     

A Compact Digitally Controlled Fuel Cell/Battery Hybrid Power Source

A compact digitally controlled fuel cell/battery hybrid power source is presented in this paper. The hybrid power source composed of fuel cells and batteries provides a much higher peak power than each component alone while preserving high energy density, which is important and desirable for many modern electronic devices, through an appropriately controlled dc/dc power converter that handles the power flow shared by the fuel cell and the battery. Rather than being controlled to serve only as a voltage or current regulator, the power converter is regulated to balance the power flow to satisfy the load requirements while ensuring the various limitations of electrochemical components such as battery overcharge, fuel cell current limit (FCCL), etc. Digital technology is applied in the control of power electronics due to many advantages over analog technology such as programmability, less susceptibility to environmental variations, and low parts count. The user can set the FCCL, battery current limit, and battery voltage limit in the digital controller. A control algorithm that is suitable for regulating the multiple variables in the hybrid system is described by using a state-machine-based model; the issues about embedded control implementation are addressed; and the large-signal behavior of the hybrid system is analyzed on a voltage–current plane. The hybrid power source is then tested through simulation and validated on real hardware. This paper also discusses some important issues of the hybrid power source, such as operation under complex load profiles, power enhancement, and optimization of the hybrid system. The design presented here can not only be scaled to larger or smaller power capacities for a variety of applications but also be used for many other hybrid power sources.     

一种内嵌EEPROM的双电源数字电位计设计

设计了一种基于嵌入式EEPROM工艺的双电源数字电位计。通过两线的I2C总线来控制电路内部EEPROM单元,调节数字电位计的输出电阻或电压。电路采用正负电源供电,同时集成了两路256个抽头可变电位计输出。由于内部集成了EEPROM单元,当电路突然掉电后依然保存抽头设置信息,重新上电后,自动恢复到掉电前电阻抽头的设定位置。该电路采用SMIC 0.18μm EEPROM工艺设计,版图面积为6.76 mm2,采用Hsim对整个电路进行仿真。仿真和测试结果表明,该电位计电路的整体非线性小于±1 LSB,级间非线性小于±0.5 LSB,输出电阻温度系数小于±100×10-6/℃,EEPROM上电恢复时间小于5 ms,可广泛应用于控制系统、参数调整和信号处理领域。     

A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers

A variable-gain low-noise amplifier with capacitive step attenuators is presented. In order to improve linearity at medium gains settings, digital gain control is performed using a current-splitting technique at the cascode transistors. The fabricated LNA shows an IIP3 increase with constant OIP3, from -1.1 dBm at 25.8 dB gain to 3.5 dBm at 21.2 dB gain. Using capacitive attenuator control, a wide gain range of over 42.7 dB is achieved. Using a 0.5-mum BiCMOS process, the proposed LNA shows an NF of 1.5 dB at 650 MHz and a power consumption of 15.4 mW under 2.9 V supply voltage. The fabricated tuner-IC, including the proposed LNA, satisfies all requirements pertinent to DVB-H reception, with sufficient margins for practical integration. Under typical DVB-H reception scenarios involving strong interferers, measurement results and analytical calculations showed good consistency at various gain settings.     

A New Automatic Constant Current Stimulator and Its Biological Applications

An instrument capable of constant current stimulation of biological preparations is described. The device can be automatically programmed in an on-line manner by a digital computer or special purpose logic. Experiments are freed of the time consuming and error producing task of continually monitoring experimental situations. Several biological uses of this instrument are discussed.     

Small-Signal$z$-Domain Analysis of Digitally Controlled Converters

As the performance of microcontrollers has increased rapidly during the last decade, there is a growing interest to replace the analog controllers in low power switching converters by more complicated and flexible digital control algorithms. Compared to high power converters, the control loop bandwidths for converters in the lower power range are generally much higher. Because of this, the dynamic properties of the uniformly-sampled pulse-width modulators (PWMs) used in low power applications become an important restriction to the maximum achievable bandwidth of the control loop. Though frequency- and Laplace-domain models for uniformly-sampled PWMs are very valuable as they improve the general perception of the dynamic behavior of these modulators, the direct discrete design of the digital compensator requires a$z$-domain model for the combination modulator and converter. For this purpose a new exact small-signal$z$-domain model is derived. In accordance with the zero-order-hold equivalent commonly used for “regular” digital control systems, this$z$-domain model gives rise to the development of a uniformly-sampled PWM equivalent of the converter. This$z$-domain model is characterized by its capability to quantify the different dynamics of the converter for different modulators, its ease of use and its ability to predict the values of the control variables at the true sampling instants of the real system.     

CMOS DAC充当数控分压器

数字电位器在可接受8位分辨率的应用中,可作为极佳的数控分压器,例如Analog Devices的AD5160。本篇设计实例介绍在需要更高分辨率的应用中如何使用CMOS DAC作为分压器。