A 3.3-V 12-ns 16-Mb CMOS SRAM

A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with a 0.4-μm process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²     

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6-μm N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V_pp of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 μm×1.75 μm and 7.18 mm×17.39 mm, respectively     

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators     

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.<>     

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb×8, 4-Mb×4, 8-Mb×2, or 16-Mb×1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect     

A 9-ns 16-Mb CMOS SRAM with offset-compensated current senseamplifier

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35-μm CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented     

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm², in spite of a 1.3-μm lithography level     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

A 60-ns 16-Mb flash EEPROM with program and erase sequencecontroller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm×2.0 μm and a chip size of 6.5 mm×18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process     

A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation     

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle     

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm² has been fabricated using a 0.4-μm N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 μm×1.7 μm each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

A 15-ns 4-Mb CMOS SRAM

A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (×4 or ×1) bit organization has been developed based on a 0.55-μm triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55-μm CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either ×4 or ×1 can be selected purely electrically, and does not require any pin connection procedure     

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported     

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-μm² high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-μm CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm×7.4 mm (29 mm²)     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns