Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits

Over the last decade, SiGe HBT BiCIMOS technology has matured from a laboratory research effort to become a 50/65-GHz fT/fmax silicon-based 0.5-μm BiCMOS production technology. This progress has extended silicon-based production technology into the multigigahertz (multi-GHz) and multigigabits-per-second (multi-Gb/s) range, thus, opening up an array of wireless and wired circuit and network applications and markets. SiGe circuits are now being designed in the same application space as GaAs MESFET and HBTs, and offer the yield cost, stability and manufacturing advantages associated with conventional silicon fabrication. A wide range of microwave circuits have been built in this technology including 5.8-GHz low-noise amplifiers with 1-V supply, up to 17-GHz fully monolithic VCOs with excellent figures of merit, high-efficiency 2.4-GHz power devices with supply voltage of 1.5 V, and move complicated functions such as 2.5/5.0-GHz frequency synthesizer circuits as well as 10/12.5-Gb/s clock and data recovery PLLs. This paper focuses on several key circuit applications of SiGe BiCMOS technology and describes the performance improvements that can be obtained by its utilization in mixed-signal microwave circuit design. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBTs with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications     

Low-power BiCMOS circuits for high-speed interchip communication

A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-μm BiCMOS technology are also presented     

A unified theory for mixed CMOS/BiCMOS buffer optimization

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is the delay can be expressed as Af+B, where A and B are coefficients. The optimum fan-out f/sub OPT/ is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NANDs and NORs in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.<>     

CMOS/BiCMOS mixed design using tabu search

The problem of optimising mixed CMOS/BiCMOS circuits is solved using a tabu search. Only gates on critical sensitisable paths are considered. This strategy leads to a circuit speed improvement of >20% with a <3% increase in the overall circuit capacitance. Comparison and experimental results are presented     

Low-power CMOS current conveyor

A novel second-generation CMOS current conveyor based on a new adaptive biasing technique is proposed. It is shown that the use of this circuit offers an excellent performance and leads to a significant reduction in the standby power dissipation. PSPICE simulation results, assuming 0.5 μm CMOS process, are also given     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

Low-power CMOS threshold-logic gate

A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

CMOS current-mode integrating receivers for Gbytes/s parallel links

This paper presents the design of fully differential current-mode integrating receivers for Gbytes/s parallel links. Both class A and class AB configurations are considered. The proposed receivers consist of a transimpedance front-end that provides a low and tunable matching impedance to the channels to accommodate current-mode signaling, an integrating stage that acts as a low-pass filter to suppress the transient disturbances coupled to the channels and receiver, and a regenerative sense amplifier to amplify the output voltage of the preceding integrator to full swing. The class AB configured sense amplifier provide a voltage gain that is twice that of class A sense amplifier, enabling a fast sensing and latching. The proposed receiver has been implemented in UMC , 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Simulation results demonstrate that the proposed class current-mode integrating receivers provide full output voltage swing when the data rate is 2.5 Gbyte/s.     

Multiband monolithic BiCMOS low-power low-IF WLAN receivers

This letter presents the design, implementation, and measurements of two monolithic low-IF receivers compliant with the main WLAN standards. The first receiver targets the three 5GHz U-NII bands, while the second allows dual-band operation in the 2GHz and 5GHz bands. Fabricated in a 47GHz-f/sub t/ BiCMOS technology, both consist of a low-noise preamplifier, two matched active singly-balanced mixers and two polyphase filters, used to generate quadrature LO signals and provide image-rejection. The single-band receiver exhibits 25 dB of conversion gain, 8.9 dB of NF and -19 dBm of P/sub 1 dB/, while consuming 19 mW. The dual-band receiver shows similar performances in the 5GHz band, and extends its operation in the 2GHz band, achieving 33.4dB of conversion gain, 4.1dB of NF and -26dBm of P/sub 1 dB/, while consuming 14.9mW.     

Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossoverbelow 2.5-V supply

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2-μm technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5-μm technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-μm gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V     

新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

Low-power BiCMOS op-amp with integrated current-mode charge pump

An operational amplifier with an integrated current-mode charge pump is presented. This operational amplifier functions with a 4-μA single-supply above-the-rail input and rail-to-rail output. Having an integrated charge pump greatly simplifies the amplifier design while providing an increased dynamic range over other rail-to-rail amplifiers. The current-mode charge pump limits the power loss associated with feedthrough current found in most voltage mode designs. The resulting amplifier, designed with a dual-well BiCMOS process, achieves a bandwidth of 54 kHz while consuming less than 10 μW     

Low-power design techniques for high-performance CMOS adders

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 μm CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V     

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10⁻¹² when the input current amplitude (I_in) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10⁻¹² when I_in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm², respectively.     

Low-power and area-efficient PSK demodulator for wirelessly powered implantable command receivers

A phase shift keying demodulator featuring miniaturisation and ultra-low power is presented. By taking advantage of a high signal-to-noise ratio on wirelessly power-combined data transmission, the demodulation can be performed without the carrier recovery circuits requiring phase lock loop, making the design quite competitive with those currently demonstrated in the literature.     

Area-efficient CMOS transimpedance amplifier for optical receivers

In this letter, a broadband area-efficient transimpedance amplifier (TIA) for optical receivers is designed using a standard 0.18 μm CMOS technology. A new shunt–shunt peaking technique is used at the input transimpedance stage, which is followed by a gain stage and a capacitive degeneration stage. The amplifier achieves a wide bandwidth with only one inductor; hence a smaller silicon area is maintained. The proposed TIA has a measured transimpedance gain of 50 dB Ohm and a −3 dB bandwidth of 6.5 GHz for 0.25 pF input photodiode capacitance. It consumes DC power of 14 mW from a 1.8 V supply voltage and occupies only 0.09 mm² silicon area.     

Parametric macromodels of differential drivers and receivers

This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link.     

Integrated Low-Dimensional Semiconductors for Scalable Low-power CMOS Logic

Scalable nanoelectronics with energy-efficient logic technology is crucial for next-generation edge devices. Low-dimensional semiconductors, such as transition metal dichalcogenides and single-walled carbon nanotubes (SWCNTs), have tunable properties with reduced short-channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal-oxide-semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero-CMOS inverters by the integration of n-type monolayer MoS₂ and p-type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer-scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer-scale integration of low-dimensional materials for low-power nanoelectronics.