峰值电流模式控制的非理想Buck变换器的建模

在 Ridley 峰值电流模式控制的 Buck 变换器模型的基础上,提出一个包含传导损耗的修正模型.运用平均开关建模法,建立非理想PWM开关的非线性大信号平均模型.包含全部寄生电阻和二极管的正向压降.围绕某一稳态工作点,扰动并线性化平均模型,导出非理想Buck变换器的功率级在连续工作模式下的直流模型和线性小信号模型.在此基础上.修正峰值电流模式控制部分的小信号模型参数.最终建立整个峰值电流模式控制的非理想Buck变换器的线性小信号模型.推导小信号动态的解析结果.给出修正的补偿斜坡信号斜率.在Simetrix/simplis开关电源软件包中进行了仿真分析,结果显示新模型能更准确地预测系统性能.     

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation(PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode(DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator(DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals.The chip is manufactured in 0.13μm CMOS technology and the chip area is 1.21 mm~2.Experimental results show that the conversion efficiency is high,being 90%at 200 mA and 67%at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability.     

A general technique for derivation of average current mode controllaws for single-phase power-factor-correction circuits without inputvoltage sensing

This paper presents a general technique to derive average current mode control (CMC) laws without input voltage sensing to achieve high power factor for single-phase topologies operating in continuous conduction mode (CCM). The control laws are derived based on the steady-state input-output voltage relationships and the CCM large-signal averaged pulsewidth modulation (PWM)-switch model. Using this methodology, average CMC laws with linear PWM waveforms are discovered for commonly used single-phase power stage topologies such as boost, flyback, SEPIC, and buck/boost. Conventional three-loop-controlled average CMC converters can now be controlled with a two-loop architecture. Hardware results for a boost power factor correction (PFC) and simulation results for flyback, SEPIC, and buck/boost topologies verify operation. The small-signal models of the current loop and voltage loop are derived for the boost topology and are used for control loop design. Input current harmonic distortion measurements demonstrate improved performance compared to the conventional three-loop control technique     

采用分段式自适应PWM/PFM调制的Buck型DC-DC转换器设计北大核心

为了在轻重负载条件下获得更高的转换效率，采用分段式结构和导通电阻更小的NMOS作为输入级，并采用PWM/PFM双调制方式，设计了一种Buck型DC-DC转换器。为解决PWM/PFM调制信号切换问题，采用零电流检测方式进行切换。利用断续导通模式(DCM)和连续导通模式(CCM)下端NMOS管导通时电感电压的不同，检测下端NMOS在导通时电感电压大于零的周期。当电感电压大于零的周期大于2时，则处于DCM模式并自动采用PFM调制模式，关闭一部分功率管以减小开关频率和功率管寄生电容，优化轻载效率；反之则处于CCM模式并采用PWM调制。仿真结果表明，在负载电流10～1 000 mA范围内，该电路可以在两种调制模式平稳切换，在800 mA时峰值效率可提升到96%以上。     

PWM型DC-DC LED驱动电路的研究与设计

采用PWM型DC-DC降压拓扑电路结构和闭环恒流控制,设计了LED驱动电路,其工作在CCM模式。该LED驱动电路选用LM2575作为PWM控制芯片,并制作了该电路的实际电路板,其外围元件较少,电路结构简单,适用于中小型LED负载驱动。通过理论分析得到电路元件和各个节点的性能参数,并应用Simulink对DC-DC降压拓扑电路进行仿真。经调试与测量表明,该电路的电气性能良好,负载输出电压纹波在±0.1%以内,功率效率达到45.5%。     

Open-loop power-stage transfer functions relevant to current-mode control of boost PWM converter operating in CCM

This paper presents the analysis of open-loop power-stage dynamics relevant to current-mode control for a boost pulsewidth-modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM). The transfer functions from input voltage to inductor current, from duty cycle to inductor current, and from output current to inductor current are derived. The delay from the MOSFET gate drive to the duty cycle is modeled using a first-order Pade/spl acute/ approximation. The derivations are performed using an averaged linear small-signal circuit model of the boost converter for CCM. The transfer functions can be used in modeling the complete boost PWM converter when current-mode control is used. The theory was in excellent agreement with the experimental results, enforcing the validity of the transfer functions derived.     

Dynamics analysis and controller synthesis forzero-voltage-transition PWM power converters

A small signal model for zero-voltage-transition pulse width modulation (ZVT-PWM) buck converters is proposed in this paper. It shows that the ZVT-PWM buck converter exhibits better dynamical behavior than the conventional PWM buck converter. Based on the derived model consisting of line voltage disturbances and load variations, μ-synthesis is applied for a robust controller design to achieve performance requirement. In addition, a classical controller and a sliding mode controller with modified integral variable structure are also designed for performance comparisons. Finally, simulation and experimental results are presented to verify the requirement for robust performance of ZVT-PWM converters     

Sliding mode control and stability analysis of buck DC-DC converter

This paper is proposed to deal with the voltage regulation of buck DC-DC converter based on sliding mode control (SMC) technology. A buck DC-DC converter with parasitic resistance is inherently a bilinear system possessing inevitable uncertainties, such as variable resistive load and input disturbance. First, the buck DC-DC converter is modified into an uncertain linear model. Then, SMC technology is adopted to suppress the input disturbance and reduce the effects from the load variation. In addition, the continuous conduction mode (CCM) for normal operation can be guaranteed by the design of sliding function. Finally, experimental results are included for demonstration.     

Duty cycle generator for average model of buck converter withcurrent-mode control-using analog behavioral modeling of PSpice

This paper presents a duty cycle generator for an average model of buck converter with current-mode control, which can simultaneously deal with both the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM). First, a duty cycle generator is mathematically derived, considering the transient-state of the current-loop. This technique plays an important role when the operating modes are changed under a considerable amount of step load change. Second, taking advantage of the analog behavioral modeling of PSpice, duty cycle generators for both the time and frequency domain analyses are built into a PSpice file. The accuracy of these models is verified through the computer simulations, which is compared to the actual circuit for the time domain analysis and the small signal model for the frequency analysis     

Voltage loop of boost PWM DC-DC converters with peak current-mode control

A new transfer function from control voltage to duty cycle, the closed-current loop, which captures the natural sampling effect is used to design a controller for the voltage-loop of a pulsewidth modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM) with peak current-mode control (PCM). This paper derives the voltage loop gain and the closed-loop transfer function from reference voltage to output voltage. The closed-loop transfer function from the input voltage to the output voltage, or the closed-loop audio-susceptibility is derived. The closed-loop transfer function from output current to output voltage, or the closed loop output impedance is also derived. The derivation is performed using an averaged small-signal model of the example boost converter for CCM. Experimental verification is presented. The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived.     

Improved small-signal analysis for the phase-shifted PWM power converter

A closed form cycle by cycle analysis forms the basis for a new zero-voltage switching (ZVS) phase-shifted PWM (PSPWM) full bridge power converter small-signal model. The paper derives the small-signal response equations. The PSPWM converter has an implicit "slew interval," making the converter dynamics difficult to analyze using traditional averaging techniques. The converter control to output transfer function under continuous conduction mode operation and using voltage-mode control does not exhibit a second order pole associated with the output L-C filter, making it different from a conventional PWM converter. This new PSPWM converter model shows that the output L-C filter is separated into two real poles, with one pole held at constant frequency independent of operating conditions. A characteristic pole depends only upon the converter switching frequency and inductor values. This characteristic pole is fundamental to understanding the PSPWM converter natural and forced responses. The new small-signal model is shown to be in excellent agreement with experimental results.     

一种基于自适应峰值电流检测的模式切换电路北大核心

在降压转换器中，为了在不同的负载情况下获得高效率，常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态，同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽，减小功率管的栅极电容，提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路，用于产生模式切换信号，其原理是监控峰值电流的变化，产生峰值电压，将峰值电压与参考电压进行比较，得到模式切换信号，以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明，在负载电流0.5～500 mA范围内，该电路可以在两种调制模式之间平稳切换，其峰值效率可提升到94%以上。     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

A buck quadratic PWM soft-switching converter using a single activeswitch

High-switching frequency associated with soft commutation techniques is a trend in switching converters. Following this trend, a buck pulsewidth modulation (PWM) converter is presented. The DC voltage conversion ratio of this converter has a quadratic dependence on duty cycle, providing a large stepdown. This new buck quadratic PWM soft-single-switched converter, having only a single active switch, provides a high efficient operating condition for a wide load range at high-switching frequency. In order to illustrate the operating principle of this new converter, a detailed study including theoretical analysis, relevant equations and simulation, and experimental results is carried out     

Modeling PWM DC/DC converters out of basic converter units

An alternative approach to modeling pulsewidth-modulated (PWM) DC/DC converters out of basic converter units (BCUs) is presented in this paper. Typical PWM DC/DC converters include the well-known buck, boost, buck-boost, Cuk, Zeta, and Sepic. With proper reconfiguration, these converters can be represented in terms of either buck or boost converter and linear devices, thus, the buck and boost converters are named BCUs. The PWM converters are, consequently, categorized into buck and boost families. With this categorization, the small-signal models of these converters are readily derived in terms of h parameter (for buck family) and g parameter (for boost family). Using the proposed approach, not only can one find a general configuration for converters in a family, but one can yield the same small-signal models as those derived from the direct state-space averaging method. Additionally, modeling of quasi-resonant converters and multiresonant converters can be simplified when adopting the proposed approach     

一种新型软开关BUCK变换器

根据传统硬开关电源引起的不良影响,提出了一种新型软开关BUCK变换器,使得高低桥MOSFET管都能在不管是轻负载或者重负载情况下达到ZVS状态.在连续导电模式（CCM）和高负载电流情况下,上桥MOSFET管开通,下桥MOSFET管侧的二极管在死区时间内导电,这样就造成了上桥MOSFET管的开关损耗.新型软开关BUCK变换器在传统BUCK变换器的基础上加入了电感和电容,在外加电感电容的情况下,在CCM下的死区时间内的电感电流可以有效地从下桥二极管整流到上桥二极管中.根据仿真结果和工作模式分析验证其性能.     

Digital control of a voltage-mode synchronous buck converter

A digital control algorithm capable of separately specifying the desired output voltage and transient response for a synchronous buck converter operating in voltage mode was developed. This algorithm is based on superimposing a small control signal onto a voltage reference at each switching cycle to cancel out the perturbations. A zero steady-state error in the output voltage can be obtained with the aid of additional dynamics to allow the controller to track a load change and update the reference to a new load state. The specifications of the control algorithm are achieved by pole placement using complete state feedback. The control algorithm was implemented on a digital signal processor (DSP)-controlled synchronous buck converter.     

An improved sampled-data current-mode-control model which explainsthe effects of control delay

A new sampled-data model for the current-mode controlled buck converter includes for the first time the effects of delay in the pulse-width-modulator (PWM). Modified z-transforms are used in this new model for constant frequency trailing-edge modulation. Realistic amounts of delay are found to be particularly significant when the buck converter is operating in the continuous conduction mode near the discontinuous conduction mode boundary. The new model is used to predict the loop gain measurements obtained with the “digital modulator” and with conventional measurement techniques. It is shown that conventional loop gain measurement techniques are insufficient to measure the loop gain in this region of operation. It is also shown that the digital modulator can add a significant amount of delay, thereby altering the loop gain of the circuit being measured. Unlike the case of a continuous system, PWM delay is found to significantly alter the low-frequency loop gain magnitude of this sampled-data system. The new model predicts the boundary condition for sub-harmonic instability, and reduces to Ridley's current-mode control model for the case of zero delay. Experimental corroboration is presented     

Buck型变换器的线性化小信号补偿前馈控制

为减小由输入电源扰动引起的输出电压工频纹波,改善DC/DC变换器动态性能,根据平均变量建模思想,为电压型PWM控制的Buck型变换器建立连续导电工作模式（CCM）下统一的平均变量等效电路。分析等效电路并根据前馈控制的不变性原理提出Buck型变换器针对输入电压扰动的线性化小信号补偿前馈控制原理及实现方法,采用该方法的Buck型变换器可快速补偿输入电压扰动,加快变换器在输入电压扰动时的动态调节过程,显著减小输出电压中包括工频在内的低频纹波,改善变换器的动态性能。仿真研究结果验证了文中线性化小信号补偿前馈控制原理、方法及其分析的正确性。