Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints ofwafer level chip scale package on buildup microvia printed circuit board

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

Solder joint crack propagation analysis of wafer-level chip scalepackage on printed circuit board assemblies

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

LGA焊点形态对焊点寿命影响的有限元分析

通过Surface Evolver软件对LGA焊点进行了三维形态预测,利用有限元数值模拟对LGA焊点在热循环条件下寿命进行了分析。研究了热循环条件下LGA焊点的应力应变分布规律,随着焊点远离元件的中心位置焊点所受到的等效应力、等效应变和塑性应变能密度逐渐增大,从而得出处于外面拐角的焊点最先发生失效的结论。基于塑性应变范围和Coffin-Manson公式计算了焊点热疲劳寿命;找出了LGA焊点形态对焊点寿命的影响规律,模板厚度一定时PCB焊盘尺寸小于上焊盘时LGA焊点的热疲劳寿命与PCB焊盘尺寸成正比,大于上焊盘时成反比,大约相等时焊点寿命最大。当PCB焊盘和模板开孔尺寸固定时,通过增大模板厚度来增加焊料体积在一定程度上可提高LGA焊点的热疲劳寿命,但是模板厚度增大到一定值时LGA焊点寿命会逐渐降低。     

Thermally induced deformation of solder joints in real packages: Measurement and analysis

The paper presents a hybrid experimental and analytical approach to track the deformation of solder joints in an electronic package subject to a thermal process. The solder joint strain is directly measured using a computer vision technique. The strain measurement is analyzed following an approach that is devised based on an established solder constitutive relation. The analysis leads to the determination of the solder joint stress and in turn, to the separation of the elastic, plastic and creep strain from the measured total strain. The creep strain rate and stress–strain hysteresis loop are also obtained. Two case studies are presented to illustrate the applications and to show the viability of the approach. Each case involves a resistor package with SAC (Sn95.5Ag3.8Cu0.7) solder joints, which is subjected to a temperature variation between ambient and 120 °C. The results confirm that shear is a dominant strain component in such solder joints. The shear strain varies nearly in phase with the temperature whereas the shear stress exhibits a different trend of variation due to stress relaxation. The peak shear stress of around 10 MPa to 15 MPa are found, which occur at near 70 °C in both cases, when the temperature ramps up at approximately 3 °C/min. The creep shear strain goes up to 0.02 and accounts for over 80% of the total shear strain. The creep strain rate is in the order of magnitude of 10⁻⁵ s⁻¹. Responding to the temperature cycling with such moderate rate, the creep strain shows modest ratcheting while the stress–strain hysteresis stabilizes in two cycles.     

WLCSP中微焊球结构尺寸对其热应力的影响

晶圆级芯片尺寸封装(WLCSP)微焊球结构尺寸对其热机械可靠性有重要的影响。通过二维有限元模拟筛选出对WLCSP微焊球及其凸点下金属层(UBM)中热应力影响显著的参数,采用完全因子实验和多因子方差统计分析定量评估各种因子影响的显著性,最后建立三维模型,用子模型技术研究关键尺寸因子对热应力变化的影响。研究发现,焊球半径是影响焊球热应力的最关键尺寸因子,电镀铜开口和铜焊盘厚度对焊球热应力的影响也较显著;钝化层开口和焊球半径是影响UBM热应力的最关键尺寸因子。随着焊球半径增大,焊球热应力减小。     

Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100 mm² without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter.     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

晶圆尺寸级封装器件的热应力及翘曲变形

晶圆尺寸级封装(WLCSP)器件的尺寸参数和材料参数都会对其可靠性产生影响。使用有限元分析软件MSCMarc,对EPS/APTOS生产的WLCSP器件在热循环条件下的热应力及翘曲变形情况进行了模拟,分析了器件中各个尺寸参数对其热应力及翘曲变形的影响。结果表明:芯片厚度、PCB厚度、BCB厚度和上焊盘高度对WLCSP的热应力影响较为明显。其中,当芯片厚度由0.25mm增加到0.60mm时,热应力增加了21.60MPa;WLCSP的翘曲变形主要受PCB厚度的影响,当PCB厚度由1.0mm增加到1.60mm时,最大翘曲量降低了20%。     

Quality and reliability of high aspect-ratio blind microvias formed by laser-assisted seeding mechanism in PCB

The laser-assisted seeding (LAS) mechanism should be able to plate microvias with a high aspect ratio that may not be feasible by conventional electroless plating due to the small via geometry. In particular, the plating of microvias with a high aspect ratio close to one is difficult due to the limited accessibility of chemical solution to the via internal wall surface in conventional plating technology. LAS is a promising alternative. The objectives of this paper are to report the deposition mechanism of a thin copper film layer (laser-assisted seeding) on printed circuit board (PCB) microvias dielectric and to study the quality and reliability of the microvias produced by this mechanism. Results find that the microvias produced by LAS have acceptable quality and are as reliable as that formed by conventional electroless plating technology. The hole wall of the microvia was covered with deposited copper, and the thickness of which was found related to some LAS parameters. A set of experimental best LAS processing conditions is also given.     

An evaluation of the lap-shear test for Sn-rich solder/Cu couples: Experiments and simulation

The lap-shear technique is commonly used to evaluate the shear, creep, and thermal fatigue behavior of solder joints. We have conducted a parametric experimental and modeling study, on the effect of testing and geometrical parameters on solder/copper joint response in lap-shear. It was shown that the farfield applied strain is quite different from the actual solder strain (measured optically). Subtraction of the deformation of the Cu substrate provides a reasonable approximation of the solder strain in the elastic regime, but not in the plastic regime. Solder joint thickness has a profound effect on joint response. The solder response moves progressively closer to “true” shear response with increasing joint thickness. Numerical modeling using finite-element analyses were performed to rationalize the experimental findings. The same lap-shear configuration was used in the simulation. The input response for solder was based on the experimental tensile test result on bulk specimens. The calculated shear response, using both the commonly adopted far-field measure and the actual shear strain in solder, was found to be consistent with the trends observed in the lap-shear experiments. The geometric features were further explored to provide physical insight into the problem. Deformation of the substrate was found to greatly influence the shear behavior of the solder.     

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

PCB粘弹性对QFN焊点可靠性的影响

基于动态拉伸DMA实验所获得的FR—4PCB的蠕变柔量曲线,用广义Maxwell模型表征了PCB的粘弹性蠕变松弛特性。通过有限元软件MSC Marc分别模拟了基于PCB弹性和粘弹性两种不同性质下,QFN器件在–55～+125℃热循环条件下的应力应变,并利用修正后的Coffin-Masson方程分别计算了它们的热疲劳寿命。结果表明,基于粘弹性条件下QFN焊点可靠性模拟结果更接近实际情况。     

Thermal cycling aging effects on microstructural and mechanicalproperties of a single PBGA solder joint specimen

This paper reports on an experimental study on how thermal cycling aging exposure changes the solder joint microstructure, intermetallic layer thickness and the residual shear strength and fatigue life in a single plastic ball grid array (PBGA) solder joint specimen. The single BGA solder joint specimen was specially designed to evaluate the microstructure and mechanical properties of three different batches of solder joint after subjected to 0, 500, 1000, and 2000 cycles of thermal cycling aging (-40°C to 125°C). It is important to relate the effects of thermal cycling aging on the changes of the microstructural and intermetallic layer thickness to the residual shear strength and fatigue life of solder joints subjected to thermal cycling aging exposure. The results of this study shows that the microstructural and intermetallic development due to thermal cycling aging has a major impact on the residual mechanical and fatigue strength of the solder joint. It was noted that the solder joint shear strength and residual fatigue life degrades with exposure to thermal cycling aging     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. By using the solder ball shear test, the stress/strain-released behavior in the SOR structure is investigated in this research. On the other hand, a three-dimensional nonlinear finite element (FE) model for the ball shear test is established to assist the design of the package. The force-displacement curves from the FE analysis are compared with the experimental results to demonstrate the accuracy of the simulation. Likewise, the issue from element mesh density is also discussed herein. The investigation reveals that the SOR structure could highly decrease the damage in solder bumps from the ball shear test. Furthermore, the transferred stress/strain in the interconnect near the contact pad could be diminished through a suitable layout of redistribution lines.