基于片上网络众核系统容错技术研究

基于片上网络的众核系统已经广泛应用在各个领域之中.用户对系统性能和系统可靠性的需求越来越高.文中对众核系统和片上网络容错技术基础进行介绍,针对众核系统软错误和硬错误分析现有的几种典型的众核系统冗余容错方法,比较了其性能差异.在总结了现有技术不足的基础上进一步分析了该领域未来的研究趋势.     

数据驱动片内多核通信结构

针对当前条件下多核处理器遇到的通信瓶颈问题,设计了一种采用数据驱动机制的片内多核通信结构,该结构包括数据驱动模块和片上路由器.数据驱动模块用来进行数据完备性检测;片上路由器则实现处理器核间的通信及"簇"间通信.在Altera公司的CycloneIII开发板上使用NIOS软核构建了多核系统进行了验证.实验结果表明,本设计可以有效的实现多核片内通信,具有很好的可扩展性.     

多核系统中NoC通讯架构的关键技术

多核处理器已经成为处理器的主流,并发展成为各种通信与媒体应用的主流处理平台。通讯结构是多核系统中的核心技术之一,核间通信的效率是影响多核处理器性能的重要指标。目前有3种主要的通讯架构:总线系统结构、交叉开关网络和片上网络。总线结构设计相对方便、硬件消耗较少、成本较低;交叉开关是适合用于构建大容量系统的交换网络结构;而片上网络是更高层次、更大规模的片上网络系统,目前可以解决多核体系结构问题,是多核系统最有前途的解决方案之一。文中在分析了NoC结构的基本原理、系统结构和功能的同时,也提供了部分单元的设计实现。     

多核处理器核间高速通讯架构的研究

多核处理器使得并行系统的结构日益复杂,已经成为处理器的主流,并发展成为各种通信与媒体应用的主流处理平台.通讯结构是多核系统中的核心技术之一,核间通信的效率是影响多核处理器性能的重要指标.目前有三种主要的通讯架构:总线系统结构、交叉开关网络和片上网络.总线结构设计相对方便、硬件消耗较少、成本较低,交叉开关是适用于构建大容...     

基于FPGA和ASIC实现的不同路由器结构的MPSoC比较

随着工艺特征尺寸的缩进,为了进一步提高数据处理速度,多核片上系统(MPSoC)成为一种必然的选择。片上网络(NoC)作为多核片上系统的通信部分,其设计影响了整个系统的性能。本文研究了2种不同的片上网络设计,探讨了路由器结构的改变对MPSoC性能的影响。对于采用低延迟优化设计的路由器,通过ModelSim仿真得到数据帧的最优传输延迟减少了6倍。同时,分别完成了该MPSoC的FPGA和ASIC实现,基于实现结果定量分析了在0.13 μm工艺尺寸下2种实现方式的面积和延时差距。结果表明,FPGA实现与ASIC实现的面积比率大约为29~33:1,延时比率大约为4.5~7.5:1。     

片上网络:新一代的片上系统结构

片上系统是使用共享或专用总线作为芯片的通信资源.由于这些总线具有一定的限制,因此扩展性较差,不能满足发展需求.在这种情况下,目前的片内互连结构将成为多核芯片的发展瓶颈.文章介绍了一种新型的片上体系结构(片上网络)来解决未来片上系统中总线所带来的不足.片上网络作为一种新的片上体系结构,可以解决片上系统设计中所带来的各种挑...     

连接主从IP核的Octagon环形网络拓扑结构

本文提出了一种连接主从IP核的Octagon环型(Master-Slave IP Core connected Octagon Loop,MSOL)拓扑结构,该拓扑结构具有8m个节点,并且每个节点分别连接主从IP核,除外层环上各核连接3个相邻节点外,内层环上各节点均与4个相邻节点连接。MSOL是一种拓扑结构简单、平面的、对称的并且具有良好扩展性的互连网络,采用基于最短路径的路由算法,在仿真实验中,对MSOL,Mesh和Cluster-Mesh网络的平均通讯延迟和平均吞吐量进行了模拟分析,结果表明MSOL互连网络较好的平衡了网络性能和成本,是一种更为优化、高效的片上网络拓扑结构。     

一种改进的高速彩票总线仲裁器

随着半导体工艺的发展,片上系统(System-on-Chip, SoC)内部集成的不同功能IP(Intellectual Property)核越来越多。各IP核通过总线方式连接,多核同时抢占总线很大地制约了片上系统的性能。高效的总线仲裁器可以解决多核抢占总线引起的冲突和竞争问题,提升片上系统性能。该文提出一种改进的高速彩票总线仲裁器。使用4相双轨协议代替时钟实现彩票抽取机制以防止彩票丢弃,采用异步流水线交叉并行的工作方式以提升工作速度。在NINP(NonIdling and NonPreemptive)模型下通过65 nm CMOS工艺的Xilinx Virtex5板级验证,相比经典彩票仲裁器和动态自适应彩票仲裁器,具有更好的带宽分配功能,有效避免撑死和饿死现象,工作速度提高49.2%以上,具有一定的功耗优势,适用于有速度要求的多核片上系统。     

片上网络拓扑结构的研究

随着SoC体系结构设计复杂度的提高,传统的总线结构已成为IP核之间通信的瓶颈。为了满足大规模集成电路发展对扩展性、能耗、面积、时钟异步、重用性、QoS等方面的需求,新的设计方法—片上网络(NoC)应运而生,它是对原有设计模式的一次革新。本文分析了NoC的技术特点以及在该领域中的关键技术,详细地对NoC中常见的拓扑结构进行了分类研究,并指出了每种拓扑结构中的优点与不足;然后通过分析每种拓扑结构的性能参数,从而对其性能进行综合的比较。     

多核MV12片上系统中断控制器的设计与实现

MV12片上系统采用特许半导体0.35μm、2层多晶硅4层金属(2P4M)混合信号工艺,工作电压3.3 V,包含1个MV11控制器内核和2个MV10控制器内核,采用多核异构系统架构,整个系统由高级微控制器总线架构相连。提出一种采用中断实现片上系统(SoC)多核间通信的解决方法,给出了一个挂载在高级外围总线(APB)上的具有控制多核中断功能的中断控制模块,该模块能够接收来自通用输入输出(GPIO)的输入,并产生中断信号,同时也能够接收MV10程序执行完成之后所产生的中断信号。通过中断的方式可以简化异构多核之间的通信,保证了异构多核系统MV12的高效性。所设计的中断控制器,可以作为知识产权(IP)核,挂载在任何采用APB的片上系统上。     

A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor

Implementation of video coding systems such as H.264/AVC and AVS on multi-core and many-core platforms is attracting much attention. The slice-level parallelism is popular in parallel video coding for its simplicity and flexibility, however, the video quality loses greatly since the partitioning of slices breaks the dependency between macro-blocks, especially on multi-core or many-core platforms. To address this problem, we propose a Macro-Block Group (MBG) parallel scheme for parallel AVS coding. In the proposed scheme, video frames are equally divided into rectangular MBG regions; each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme. Given that MBG is not syntactically supported by AVS, a vertical partitioning scheme is introduced. Additionally, we use mode confining and motion vector difference adjusting techniques to keep consistent with the standard. Two MBG parallel schemes (5 × 9 MBG partition and 8 × 7 MBG partition) are developed on a TILE64 many-core platform, where P/B frames use the MBG parallel scheme and I frames use the macro-block-level parallelism. Experimental results show that the proposed scheme of 5 × 9 MBG partition can achieve a reduction of 52% (IPPP) and 41% (IBBP) quality loss while keeping the same speed-up compared with the slice-level parallelism. With more cores employed, the scheme of 8 × 7 MBG partition gains 23.9 times of speed-up compared with the single-core implementation and achieves similar coding performance as the 5 × 9 scheme.     

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.     

A Simple Compressive Sensing Algorithm for Parallel Many-Core Architectures

In this paper we consider the l ¹-compressive sensing problem. We propose an algorithm specifically designed to take advantage of shared memory, vectorized, parallel and many-core microprocessors such as the Cell processor, new generation Graphics Processing Units (GPUs) and standard vectorized multi-core processors (e.g. quad-core CPUs). Besides its implementation is easy. We also give evidence of the efficiency of our approach and compare the algorithm on the three platforms, thus exhibiting pros and cons for each of them.     

基于成团效应的众核处理器失效核分布建模方法

随机产生失效核分布的方法不能反映众核处理器物理拓扑结构的真实状况,在评价相关拓扑重构算法的效能时有失客观性.本文针对这一现状,提出了一种基于缺陷成团效应的众核处理器失效核分布建模方法.实验表明,本方法得到的物理拓扑结构缺陷分布呈现出不同程度的成团特性,且成团效应会显著影响核级冗余技术的拓扑重构效果.     

Applying Petri Nets to Modeling of Many-Core Processor Self-Testing when Tests are Performed Randomly

Today’s many-core processors are manufactured in inherently unreliable technologies. Massively defective technologies used for production of many-core processors are the direct consequence of the feature size shrinkage in today’s CMOS (complementary metal-oxide-semiconductor) technology. Due to these reliability problems, fault-tolerance of many-core processors becomes one of the major challenges. To reduce the probability of failures of many-core processors various fault tolerance techniques can be applied. The most preferable and promising techniques are the ones that can be easily implemented and have minimal cost while providing high level of processor fault tolerance. One of the promising techniques for detection of faulty cores, and consequently, for performing the first step in providing many-core processor fault tolerance is mutual testing among processor cores. Mutual testing can be performed either in a random manner or according to a deterministic scheduling policy. In the paper we deal with random execution of mutual tests. Effectiveness of such testing can be evaluated through its modeling. In the paper, we have shown how Stochastic Petri Nets can be used for this purpose and have obtained some results that can be useful for developing and implementation of testing procedure in many-core processors.     

MST-based clustering topology control algorithm for wireless sensor networks

In this paper, we propose a novel clustering topology control algorithm named Minimum Spanning Tree (MST)-based Clustering Topology Control (MCTC) for Wireless Sensor Networks (WSNs), which uses a hybrid approach to adjust sensor nodes’ transmission power in two-tiered hierarchical WSNs. MCTC algorithm employs a one-hop Maximum Energy &; Minimum Distance (MEMD) clustering algorithm to decide clustering status. Each cluster exchanges information between its own Cluster Members (CMs) locally and then deliveries information to the Cluster Head (CH). Moreover, CHs exchange information between CH and CH and afterwards transmits aggregated information to the base station finally. The intra-cluster topology control scheme uses MST to decide CMs’ transmission radius, similarly, the inter-cluster topology control scheme applies MST to decide CHs’ transmission radius. Since the intra-cluster topology control is a full distributed approach and the inter-cluster topology control is a pure centralized approach performed by the base station, therefore, MCTC algorithm belongs to one kind of hybrid clustering topology control algorithms and can obtain scalability topology and strong connectivity guarantees simultaneously. As a result, the network topology will be reduced by MCTC algorithm so that network energy efficiency will be improved. The simulation results verify that MCTC outperforms traditional topology control schemes such as LMST, DRNG and MEMD at the aspects of average node’s degree, average node’s power radius and network lifetime, respectively.     

Reconfiguration of Logical Topologies with Minimum Traffic Disruptions in Reliable WDM-Based Mesh Networks

A wavelength division multiplexing (WDM) network offers a flexible networking infrastructure by assigning the route and wavelength of lightpaths. We can construct an optimal logical topology, by properly setting up the lightpaths. Furthermore, setting up a backup lightpath for each lightpath improves network reliability. When traffic demand changes, a new optimal (or sub-optimal) topology should be obtained by again applying the formulation. Then, we can reconfigure the running topology to the logical topology obtained. However, during this reconfiguration, traffic loss may occur due to the deletion of older lightpaths. In this paper, we consider reconfiguring the logical topology in reliable WDM-based mesh networks, and we propose five procedures that can be used to reconfigure a running lightpath to a new one. Applying the procedures one by one produces a new logical topology. The procedures mainly focus on utilizing free wavelength resources and the resources of backup lightpaths, which are not used usually for transporting traffic. The results of computer simulations indicate that the traffic loss is remarkably reduced in the 14-node network we used as an example.     

空分复用中的多芯光纤

介绍了近年来出现的光纤通信用单/多模多芯光纤(MCF)的基本特性和结构轮廓,列举了部分试验传输实例。指出人们对光纤通信容量的追求在时分、波分、偏分复用及多级调制方式的基础上,已开始将目光关注在基于MCF的空分复用(SDM)上,相信MCF的规模化商用已为时不远。     

高密度集成与单芯片多核系统及其研究进展

在体积、重量和功耗有严格约束的情况下,系统小型化遇到多种技术挑战,为了满足高密度计算和小型化的要求,高密度系统集成和单芯片多核处理器至关重要。讨论了高密度集成与单芯片多核处理器技术及其研究进展,其中包括单芯片多核处理器(CMP)、片上网络(NoC)、3D集成电路、高密度封装。提出了CMP的两个发展特征,即小核大数量和层次型簇结构。指出高密度集成设计与高密度封装设计逐渐融合,并为单芯片多核系统的物理实现提供了技术保证,为最终实现高密度计算和小型化系统提供了硬件解决方案。     

Development of novel fibers for telecoms application

This paper reviews the current situations of optical fibers used for terrestrial and submarine transmission systems as well as up-to-date R&;D on these fibers. The current fibers include standard single mode fibers (SMFs), non-zero dispersion shifted fibers (NZ-DSFs), and dispersion managed lines (DMLs). Even though these fibers show quite high and matured properties, the internet traffic is continuously growing, and around 2015–2020, it is expected that the current transmission fibers would become inadequate. To prepare for the future ultra high-capacity transmission, there are three important R&;D directions for transmission fibers. (1) Reducing non-linearity by means of enlarging Aeff and/or reducing attenuation loss. It is very important in the case of transmission systems using new multi-level signal formats. (2) Expanding the transmission band more than the current C- and/or L-Band by utilizing new transmission fibers. For example, holey fibers (HFs), which have an endlessly single mode (ESM) property, are one of the interesting candidates of the new transmission fibers. (3) Using Space Division Multiplexing (SDM) by using multi-core fibers. The multi-core fiber literally multiples the core number within a fiber dimension, which enables multiple transmission capacity per one fiber. In addition to the developments of transmission fibers, component fibers have also been studied and developed. Examples of R&;D on these component fibers will be also discussed in the latter part of this paper.