基于虚拟化技术的进程级监控

目前虚拟环境中,虚拟机管理程序VMM和客户操作系统之间相对独立,因此,VMM只能对客户操作系统的整体运行情况进行监控.但是,当客户操作系统中一个进程因某种原因导致整个客户操作系统崩溃时,VMM显得无能为力.文中将VMM对客户操作系统的监控粒度从操作系统级提升到进程级,从而增强虚拟机的安全性和稳定性.     

虚拟机的可信计算技术研究

虚拟化技术作为云计算的关键技术,提高了企业计算资源的利用率。为了保证虚拟机运行环境的完整性和安全性,基于KVM虚拟机平台提出了一种可信虚拟计算架构。解决了可信虚拟平台下虚拟身份证明密钥的私密性问题,使得信任链能够从硬件TPM延伸到客户操作系统,为虚拟机的安全提供了保障。     

DRS集群虚拟机迁移研究

在VMware虚拟化解决方案中,当客户部署的v Sphere数据中心需要进行维护时,要在不同VMware ESXi主机之间进行虚拟机迁移。若虚拟机没有运行业务,关闭虚拟机并进行虚拟机迁移则相对容易;若虚拟机有正在运行的业务,而且不能关闭,则难以进行虚拟机迁移。因此,重点运用负载均衡与轮询算法,在保证数据业务不受影响与分布式资源调度（distributed resource scheduling, DRS）集群整体性能稳定的情况下,在DRS集群中实现虚拟机迁移。     

虚拟CPU负载预测算法性能评估

准确的虚拟CPU负载预测是提高虚拟机CPU调度性能的重要前提,然而,虚拟机操作系统环境下,虚拟CPU负载预测方法需要尽可能简单、有效.针对虚拟机CPU调度应用场景,以实际CPU负载为研究对象,选取五种简单的时间序列预测算法,详细评估其虚拟CPU负载预测性能,为虚拟机CPU调度的实现提供了研究基础.结果表明,平均移动法、...     

基于OpenStack云计算的计算机教学实训平台设计与实现

传统的计算机教学实训平台一般通过使用VMware Workstation创建一系列的虚拟机,在VMware Workstation强大的组网能力下搭建复杂的网络环境来实现虚拟机之间相互通信。传统的计算机教学实训平台面临着一系列的问题,如操作系统与应用软件升级换代越来越占用计算机资源、随着时间推移计算机性能逐渐下降、学生下课后无法使用教学实训资源等。随着云计算技术的飞速发展,使用OpenStack云计算技术可以构建计算机教学实训平台,把传统虚拟机的资源从部署在学生端转移到服务器端,学生只需1台性能一般的计算机通过远程软件连接到服务器上就可以完成实训,彻底解决了计算机实训室一直需要不断地对硬件与软件升级的问题。     

分布式I／O资源虚拟化技术的研究

提出一种可有效整合和使用分布式I/O资源的新方案.该方案实现于操作系统和系统硬件之间,主要采用最新的硬件虚拟化技术,将分布于多主机的I/O资源进行虚拟化和整合,为上层客户操作系统构建一个全局虚拟I/O空间,实现客户操作系统对分布式I/O资源的全局管理和使用.该方案实现于系统软件层,性能较高、实现成本低,并且客户操作系统无需做任何修改.     

云计算业务平台的虚拟机容量规划研究

做好虚拟机容量规划是云计算业务平台建设中一项非常重要的工作。本文对虚拟机容量规划相关内容进行了研究和探讨,提出了容量规划方法、资源需求性能量化模型、资源需求与资源提供匹配的计算方法以及资源优化实施建议等。     

存储虚拟化设计与实现

虚拟化技术研究广泛应用于服务器到PC机,目前在嵌入式机载领域也有很多相关研究。存储虚拟化是虚拟化技术的关键部分,能够提供虚拟机之间的空间隔离能力,保证虚拟机之间不会出现空间访问越界,并且保证客户操作系统的MMU功能。本文在机载领域使用的硬件平台Power PC E500mc处理器上设计实现了存储虚拟化。     

基于容器技术的云计算资源合理调度方法研究

传统基于Hypervisor模型的云计算资源调度方法存在长时间得不到调度,调度性能低的问题。针对该问题,设计基于容器技术的云计算资源合理调度方法,设计了调度系统的架构以及调度流程。详细说明了虚拟机迁移时间判断流程以及被迁移虚拟机选择流程。采用Migrate方法完成虚拟机的迁移,资源统计过程通过调用Libvirt的接口实现通信,并通过近似的方式运算虚拟机CPU使用率,降低了云计算资源调度时的数据中心能耗。经过测试表明,所提方法稳定性高,总体性能优,达到了预期目标。     

试析合理分配虚拟机资源,降低整合风险

为虚拟机配置过多的资源,会浪费了其他虚拟机可能要用到的资源,而资源分配过少又势必导致虚拟机性能低下,因此,了解哪些资源会对虚拟机稳定性产生影响、合理配置虚拟机资源,降低整合风险成为了一项重要的工作。     

Virtualization: Old Technology Offers Huge New Potential

Essentially, virtualization uses a virtual machine monitor or host called a hypervisor to enable multiple operating system instances to run on a single physical server. The hypervisor can run directly on a given server's hardware platform, with the guest operating system running on a layer above the hypervisor. It can also run within an operating system, with the guest OS running on the third layer above the hardware     

Chalcogenide memory materials

The operating principles of an amorphous semiconductor non-volatile memory (ovonic memory switch) are reviewed. Methods for including the memory switch in bipolar integrated circuits with two levels of conductor are discussed. Electrical performance currently attainable from integrated memory devices of this type is outlined.     

Performance analysis of multicast replication mechanism in shared-memory switch with speedup

A multicast replication algorithm is proposed for shared memory switches. It uses a dedicated FIFO to multicast by replicating cells at receiver and the FIFO is operating with shared memory in parallel. Speedup is used to promote loss and delay performance. A new queueing analytical model is developed based on a sub-timeslot approach. The system performance in terms of cell loss and delay is analyzed and verified by simulation.     

Automated optimization for memory‐efficient high‐performance deep neural network accelerators

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high‐performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high‐performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE‐array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high‐performance DNN accelerators.     

A 90-MHz 16-Mb system integrated memory with direct interface toCPU

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. Also fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-μm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3 mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-bit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants (PDA's), personal computer systems, and embedded controller applications     

Retention Performance of Ferroelectric Polymer Film for Nonvolatile Memory Devices

For nonvolatile memory devices, capacitors with metal–ferroelectric–metal structures were fabricated using poly(vinylidene fluoride-trifluoroethylene) as a ferroelectric layer, and performance was estimated in terms of retention property. In the same thickness, the polarization retained longer as the writing pulsewidth (PW) was extended. With the same writing PW, a thicker capacitor maintained a polarized state longer. In conclusion, the performance for operating voltage, operating frequency, and data retention time is expected.      

Scalable IP lookup for Internet routers

Internet protocol (IP) address lookup is a central processing function of Internet routers. While a wide range of solutions to this problem have been devised, very few simultaneously achieve high lookup rates, good update performance, high memory efficiency, and low hardware cost. High performance solutions using content addressable memory devices are a popular but high-cost solution, particularly when applied to large databases. We present an efficient hardware implementation of a previously unpublished IP address lookup architecture, invented by Eatherton and Dittia (see M.S. thesis, Washington Univ., St. Louis, MO, 1998). Our experimental implementation uses a single commodity synchronous random access memory chip and less than 10% of the logic resources of a commercial configurable logic device, operating at 100 MHz. With these quite modest resources, it can perform over 9 million lookups/s, while simultaneously processing thousands of updates/s, on databases with over 100000 entries. The lookup structure requires 6.3 bytes per address prefix: less than half that required by other methods. The architecture allows performance to be scaled up by using parallel fast IP lookup (FIPL) engines, which interleave accesses to a common memory interface. This architecture allows performance to scale up directly with available memory bandwidth. We describe the tree bitmap algorithm, our implementation of it in a dynamically extensible gigabit router being developed at Washington University in Saint Louis, and the results of performance experiments designed to assess its performance under realistic operating conditions.     

Adaptive optimization of a time-sharing system's performance

The complex task of managing a virtual memory multiprogramming system is considered as one which can be achieved by allowing the operating system to make use of measurement data gathered on-line in the scheduling decisions it has to make. System performance optimization is achieved by continuous monitoring of critical system parameters and workload characteristics and by use of this information in a real-time adaptive feedback control policy. As a specific application of this approach, the maximization of system throughput by the regulation of the degree of multiprogramming in a virtual memory system is examined. The specific form of this performance measure as a function of the number of active processes sharing main memory is used in the design of an adaptive and statistical maximum-seeking algorithm designed to respond to abrupt changes in program locality. The data gathering and smoothing procedures and the optimization policy are then implemented in a simulator of a virtual memory time-sharing system and evaluated in simulation runs with a random and time-varying workload. These experiments are used to tune the various parameters of the algorithm and to demonstrate its ability to maintain the system at an optimal level of performance. Statistical confidence intervals for these simulation runs are given in order to provide a measure of significance to the experiments.     

VxWorks的内存配置和管理

VxWorks操作系统环境下内存配置和管理决定了VxWorks的系统性能,重点从软硬件配置、接口函数、应用优化3个方面对内存配置和管理方法进行了阐述和研究。