基于NEC单片机的电动车充电器控制系统设计

为了满足电动汽车蓄电池快速无损伤充电的要求,设计了基于NEC单片机+SG3525的充电控制系统。该控制系统采用慢脉冲快速充电方法,对动力蓄电池按给定的曲线进行高效的快速脉冲充电。对单片机控制系统外围电路和软件进行了设计。进行了蓄电池充电实验,结果表明,系统可以较好的实现对动力蓄电池的快速无损伤充电。     

电动汽车铅酸蓄电池智能充电及其策略

为提高电动汽车铅酸蓄电池寿命和续航能力,实现蓄电池高效、快速充电,设计了一种智能充电系统。硬件采用DC/DC正激变换电路实现功率的转换,同时以单片机为智能控制核心,并利用DS18B20采集电池温度。软件上根据蓄电池快速充电原理,提出一种分阶段定电流和正负脉冲相结合的新型充电控制策略。利用模块化设计方法,完成各功能模块设计,以及利用数字 PI算法实现分阶段电流恒定。实验证明,采用新型控制策略的智能充电系统对蓄电池进行充电,减少了充电时间,提高了充电效率。     

基于UC3906的太阳能充电控制器的设计

文中针对光伏发电的特点,设计了一种结构简单、性能优良的充电控制器。在传统的控制器的基础上加入了Buck—Boost变换器和蓄电池充电专用管理芯片UC3906,不仅大大提高了充电效率,并且能很好地实现蓄电池的管理,延长了蓄电池的使用时间。     

基于LabVIEW的军用铅酸蓄电池状态参数采集系统设计

实时在线测量蓄电池的状态参数可以很好地监测蓄电池的状态,指导充电电流的大小,从而缩短充电时间,提高充电效率,延长蓄电池的使用寿命,文中设计了基于LabVIEW的蓄电池状态参数采集系统,该系统可以在本地计算机上远程监控蓄电池的充电状态,从而控制充电电流的大小。     

无人值守人工电话总机电源充供电装置

<正> 目前,很多乡村(特别是偏远山区的乡村)和部队小型通信台站的人工电话总机都是用两组24V蓄电池作工作电源。蓄电池的充电、供电转换主要由人工操作,有时因检查不及时,造成蓄电池过放电或过充电,既影响了设备正常工作,又缩短了蓄电池的使用寿命。为此,我们设计了一种无人看守的人工电话总机电源充电、供电全自动切换装置。它具有如下功能:能对人工总机用的两组24V蓄电池的电压自动进行连续监视和控制切换。当蓄电池需要充电时,能自动接通充电设备的电源开始充电;当蓄电池的电压充到上限规定值时,能自动切断充电设备电源停止充电;当一组蓄电池开始充电时,能自     

大容量铅酸蓄电池充电系统的实现

针对蓄电池充电过程中出现的种种问题,设计了一种大批量,大容量铅酸蓄电池的分布式充电系统,解决了充电检测的关键技术,实现了快速充电,该系统的设计思想是基于电压,电流和温度的检测值的自适应控制方法。     

一种智能铅酸蓄电池充电器的设计

介绍了蓄电池充电特性和充电方式,设计了一种可对铅酸蓄电池实现三段式充电的低成本智能充电器设计方案,结合主电路和MCU控制电路较为详细地阐述了其控制和保护策略,并给出了该充电器的充电曲线图。     

单片机控制太阳能充电控制器

针对目前太阳能充电控制器对蓄电池的保护不够充分,蓄电池的寿命缩短这种情况,研究确定了一种基于单片机Atmega16的太阳能充电控制器的方案。本设计使用低功耗、高性能的Atmega16单片机作为核心器件对整个电路进行控制。系统硬件电路由太阳能电池充电电路、电压采集和显示电路、单片机控制电路和RS-485串口通信电路组成,主要实现对蓄电池电压的采集和显示。软件部分依据PWM（pulse width modulation）脉宽调制控制策略,编制程序使单片机输出PWM控制信号,控制信号将实现对功率开关器件MOS管开通与关断的控制,从而实现太阳能极板对蓄电池的充电控制[1]。根据控制器的要求,编制软件程序,软件实现蓄电池高效率充电,使蓄电池不过充、过放,保护蓄电池,延长蓄电池使用寿命。     

离网型风光互补系统蓄电池充电控制研究

针对离网型风光互补系统蓄电池组充电电流暂态冲击较大、充电曲线不平稳的问题,在比较分析现有蓄电池充电控制方法的基础上,选择使用先恒流后恒压的两阶段充电方式,并设计两个PID环切换的控制算法进行这两个阶段的平稳充电。仿真研究和硬件系统实验分析结果均表明：基于两个PID环切换的充电控制算法可以实现离网型风光互补系统蓄电池组的平稳充电,两个阶段的充电过程中充电电流平稳、纹波小,系统响应速度快,改善了蓄电池组的充电曲线,有望提高蓄电池的使用寿命。     

正负脉冲型电动车智能充电器的设计

从保护铅酸蓄电池、提高充电效率的角度出发,分析了目前市场上主要充电方式的弊端,设计了一种正负脉冲型电动车智能充电器。系统采用PIC16F676单片机进行控制,将普通三段式充电方式中的恒压阶段变为正负脉冲充电方式,增加了涓流充电等功能,优化了定时和自断电电路,在延长蓄电池使用寿命、缩短充电时间方面有很好的效果。     

Block-based multiperiod dynamic memory design for low data-retention power

Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN/sup 2/) steps our algorithm computes K refresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.     

A surface-charge shift register with digital refresh

A digital shift register using the surface-charge transistor structure in which adjacent rows propagate in opposite directions and which has refresh turn-around circuits at the ends of each row is described. Two process compatible refresh circuits requiring only four times the basic bit storage area have been designed, and a test circuit composed of two 16-bit shift registers that propagate in opposite directions and are connected by these circuits has been built and tested. The regeneration characteristics of these refresh circuits have been measured as a function of transfer time in both the complete and partial transfer modes (`fat zero'). Operation of one of these 32-stage shift registers and its refresh at 10 MHz is presented.     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

A refreshable analog VLSI neural network chip with 400 neurons and40 K synapses

An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals     

Influence of Battery/Ultracapacitor Energy-Storage Sizing on Battery Lifetime in a Fuel Cell Hybrid Electric Vehicle

Combining high-energy-density batteries and high-power-density ultracapacitors in fuel cell hybrid electric vehicles (FCHEVs) results in a high-performance, highly efficient, low-size, and light system. Often, the battery is rated with respect to its energy requirement to reduce its volume and mass. This does not prevent deep discharges of the battery, which are critical to the lifetime of the battery. In this paper, the ratings of the battery and ultracapacitors are investigated. Comparisons of the system volume, the system mass, and the lifetime of the battery due to the rating of the energy storage devices are presented. It is concluded that not only should the energy storage devices of a FCHEV be sized by their power and energy requirements, but the battery lifetime should also be considered. Two energy-management strategies, which sufficiently divide the load power between the fuel cell stack, the battery, and the ultracapacitors, are proposed. A charging strategy, which charges the energy-storage devices due to the conditions of the FCHEV, is also proposed. The analysis provides recommendations on the design of the battery and the ultracapacitor energy-storage systems for FCHEVs.     

A 16 384-bit dynamic RAM

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.     

钻杆输送存储式测井仪电池控制系统设计

钻杆输送无电缆存储式测井是解决大斜度井、水平井、欠平衡井等高难度测井的重要技术手段.井下仪器电池的合理使用、电池状态的监控是保证测井仪器可靠工作的关键.文中给出了钻杆输送存储式测井仪电池控制系统的硬件电路及软件关键部分设计、压力采集温漂校正方法,总结了该系统在设计及实际工程应用中体现的一些优点.该系统在胜利油田及外部油区的应用表明,电池控制系统能够确保仪器取全取准测井资料,解决了测井工程的一大技术难题.     

基于Labview的蓄电池在线监测系统设计

为了实现对蓄电池参数检测的需求,提出了一种基于Labview的蓄电池在线监测系统设计方案,并完成系统的软硬件设计。该系统的硬件部分主要用来采集蓄电池的各种参数信号,软件部分采用Labview进行编程,能够完成对其参数进行检测。实际应用表明,该系统具有操作简便、检测准确的特点,达到了设计要求。     

A 256K dynamic random access memory

A 5 V 256K/spl times/1 bit NMOS dynamic RAM employing redundancy is described. Using 2.3 /spl mu/m design rules, the cell is laid out in a folded bit line configuration having a row pitch of 6.5 /spl mu/m and a sense-amplifier pitch of 18 /spl mu/m. Tantalum silicide/polysilicon is used as the second polysilicon level to reduce the row line time constant. A storage capacitance of 60 fF and the Hi-C cell structure provides this memory with high alpha-particle insensitivity. The die measures 4.66/spl times/11.65 mm, and fits into a standard 0.3 in wide 16-pin DIP. The memory operates with 256 refresh cycles with a 4 ms refresh time. Typical RE/CE access times are 105/45 ns with an active power dissipation of 250 MW. Typical standby power is less than 20 mW. The part is compatible with the present Western Electric 5 V 64K part.     

抗单粒子翻转的双端口SRAM定时刷新机制研究

在空间辐射环境下,存储单元对单粒子翻转的敏感性日益增强。通过比较SRAM的单粒子翻转效应相关加固技术,在传统EDAC技术的基础上,增加少量硬件模块,有效利用双端口SRAM的端口资源,提出了一种新的周期可控定时刷新机制,实现了对存储单元数据的周期性纠错检错。对加固SRAM单元进行分析和仿真,结果表明,在保证存储单元数据被正常存取的前提下,定时刷新机制的引入很大程度地降低了单粒子翻转引起的错误累积效应,有效降低了SRAM出现软错误的概率。