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1.
A 10-bit 200-MHz CMOS video DAC for HDTV applications 总被引:1,自引:0,他引:1
Jiaoying Huang Yigang He Yichuang Sun Hui Liu Hui Yang 《Analog Integrated Circuits and Signal Processing》2007,52(3):133-138
This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed
10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity,
power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve
linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The
measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter
achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The
circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm2. When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply. 相似文献
2.
Jin-Park Seung-Chul Lee Seung-Hoon Lee 《Electronics letters》1999,35(24):2071-2073
This work describes a 10 b 70 MHz CMOS digital-to-analogue converter (DAC) for video applications. The proposed DAC is composed of a unit decoded matrix for 7 MSBs and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area and glitch energy. A new switching scheme for the unit decoded matrix is developed to further improve the linearity. Cascode current sources and differential switches with a new deglitching circuit improve the dynamic performance 相似文献
3.
A 14-b, 100-MS/s CMOS DAC designed for spectral performance 总被引:2,自引:0,他引:2
Bugeja A.R. Song B.-S. Rakers P.L. Gillig S.F. 《Solid-State Circuits, IEEE Journal of》1999,34(12):1719-1732
A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm 2 of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed 相似文献
4.
A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC 总被引:2,自引:0,他引:2
《Solid-State Circuits, IEEE Journal of》2008,43(11):2396-2403
5.
一种电流自校准14位、50Msample/s CMOS DAC 总被引:1,自引:1,他引:1
文章介绍一种14位、50Msample/s的电流驱动型CMOS DAC.该电路的核心由31个温度计编码的高5位电流源、15个温度计编码的中间4位电流源和5个二进制编码的低5位电流源构成.为了达到更高的静态线性度,一种新颖的电流自校准技术被提出,用来对最高5位的电流源进行自校准.这种自校准完全是在后台操作的,并不需要一个替代电流源去替代正在被校准的那一路电流源.该芯片采用0.25μm标准CMOS工艺制造,芯片面积为3.54mm2.测试结果显示芯片的静态分辨率达到12位. 相似文献
6.
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC 总被引:1,自引:0,他引:1
Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s. 相似文献
7.
Zhangming Zhu Yu Xiao Lifeng Xu Haoyu Ding Yintang Yang 《Analog Integrated Circuits and Signal Processing》2013,77(2):249-255
This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively. 相似文献
8.
An I/Q channel 12-bit 120?MS/s CMOS DAC with deglitch circuits 总被引:1,自引:0,他引:1
Jong-Kug Seon Seong-Min Ha Kwang Sub Yoon 《Analog Integrated Circuits and Signal Processing》2012,72(1):65-74
This paper describes an I/Q channel 12bit 120?MS/s DAC with deglitch circuits. The proposed DAC implemented in a 0.35???m CMOS n-well process employs three stage 4 bit thermometer decoders and deglitch circuits to minimize glitch energy and linearity error. The measurement results show a ±1.5?LSB/±1.3?LSB of INL/DNL and 31 pV·s of glitch energy. ENOB and SFDR are measured to be 10.5 bit and 71.09?dB at sampling frequency of 120?MHz and input frequency of 1?MHz with a total power consumption of 105?mW. Linearity error between I-channel DAC and Q-channel DAC is measured to be approximately 1.5?mV, i.e. the accuracy of 13 bit. 相似文献
9.
针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源... 相似文献
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12.
A 1.5-V 14-bit 100-MS/s self-calibrated DAC 总被引:2,自引:0,他引:2
Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-/spl mu/m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm/sup 2/ of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW. 相似文献
13.
A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-μm, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm2. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry 相似文献
14.
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS 总被引:1,自引:0,他引:1
Hyde J. Humes T. Diorio C. Thomas M. Figueroa M. 《Solid-State Circuits, IEEE Journal of》2003,38(5):734-740
Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s. 相似文献
15.
A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (fCLK) of 10 MHz and an output frequency (fOUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices 相似文献
16.
Shu-Yuan Chin Chung-Yu Wu 《Solid-State Circuits, IEEE Journal of》1994,29(11):1374-1380
This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-μm double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to ±1/2 LSB is within 8 ns. The chip area is 1.8 mm×1.0 mm 相似文献
17.
异步逐次比较模数转换器由于其高能效和中高性能在近年来得到了广泛的关注。其设计性能的主要瓶颈在于其单位电容的大小。本文提出了一种三维结构的金属-氧化层-金属电容,其单位电容大小仅为1 fF。该电容形似伞状,以此实现快速建立的性能需求。作者将该电容和目前国际顶尖的定制化三维电容结构进行了比较。为了验证该电容的有效性,作者设计了一个基于该电容的6位电容型数模转换器,基于TSMC 1P9M 65nm LP CMOS工艺。该数模转换器在100MS/s的工作速度下功耗为0.5mW,其中没有包含以可测性为目的的源级跟随器。静态性能测试结果显示该数模转换器的INL小于 /- 1LSB,DNL 小于 /- 0.5 LSB,从而证明了该电容的有效性。 相似文献
18.
介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。 相似文献
19.
An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate. 相似文献
20.
An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the... 相似文献