An efficient VLSI architecture for 2-D wavelet image coding withnovel image scan

A folded very large scale integration (VLSI) architecture is presented for the implementation of the two-dimensional discrete wavelet transform, without constraints on the choice of the wavelet-filter bank. The proposed architecture is dedicated to flexible block-oriented image processing, such as adaptive vector quantization used in wavelet image coding. We show that reading the image along a two-dimensional (2-D) pseudo-fractal scan creates a very modular and regular data flow and, therefore, considerably reduces the folding complexity and memory requirements for VLSI implementation. This leads to significant area savings for on-chip storage (up to a factor of two) and reduces the power consumption. Furthermore, data scheduling and memory management remain very simple. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches, reading the input data line by line     

JPEG2000中小波滤波器的定点分析及其VLSI实现

对JPEG2 0 0 0中推荐的 5 /3整数滤波器和 9/7实数滤波器进行了硬件实现时所需要的有限精度分析 ;确定了小波变换过程中各个参数的最佳数据宽度 ,还确定了整个变换系统的数据通路的数据宽度。基于lifting的小波变换的特点结合嵌入式延拓算法提出了两种小波变换———折叠结构和长流水线结构 ;对两种结构进行了分析比较。最后 ,对折叠结构和相关的其它结构在所需存储单元的数量、存储单元的访问次数、处理能力以及功耗等方面进行了分析比较 ,可以看出文中提出的结构在性能上有明显优点。     

一种高效的三维DWT VLSI结构设计方法

文中通过深入研究三维离散小波变换(3D DWT)核心算法并根据序列图像编码的特点,设计并实现了一种适合硬件实现的高效的三维小波变换VLSI结构。编写了相应verilog模型,并进行了仿真和逻辑综合。仿真结果表明行列滤波并行处理并采用流水线设计方法,加快了运算速度,有效降低了片内存储容量。     

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated.     

Synthesis of folded pipelined architectures for multirate DSPalgorithms

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms     

一种高性能9/7离散小波变换滤波器的硬件设计

基于提升格式的离散小波变换比传统的基于卷积的运算量少,易于VLSI实现。本文提出了一种基于提升格式,高效实时实现JPEG2000中9/7双正交离散小波变换滤波器的VLSI结构设计方法。该方法所设计的结构,在保证同样的精度下,减少了运算量,整体运算速度高,硬件花费少,存储需求低,硬件利用率达到100%。本文用Verilog HDL对系统进行硬件描述,并选用Xilinx公司的XCV50e-cs144-8器件在ISE4.1环境下实现了综合。     

Design and analysis of a self-testing-and-repairing random access memory “STAR–RAM” with error correction

This paper presents the philosophy and design of a fault-tolerant dynamically-reconfigurable random access memory (RAM) system with a built-in Self-Testing-And-Repairing “STAR” engine. The STAR engine, supported by SEC–DED capability, provides on-line fault detection, correction, analysis and repair without destroying useful data stored in the memory. Reliability analysis of the presented system has been accomplished using a SMART simulation approach[1], and results show significant reliability enhancement over SEC–DED RAM designs. The memory system employs a hardware parallel address-comparison mechanism for rapid processing of incoming addresses during normal read/write operations to minimize memory access delay. The flexible STAR architecture and the low hardware overhead enables utilization of the proposed approach in VLSI memory chips as well as in WSI and large memory modules.     

2D DWT VLSI architecture for wavelet image processing

A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size     

离散小波变换的VLSI实现

离散小波变换已广泛应用于信号处理中。然而,实时小波变换需要大量运算,因此,专用小波变换芯片的设计已成为信号处理中的关键技术。文章提出了一种小波变换递归金字塔算法的VLSI结构,采用一组输入延迟单元和一个控制单元,用一组并行滤波器完成了小波变换。编写了相应的Verilog HDL模块,并进行了仿真和逻辑综合。     

VLSI architectures for discrete wavelet transforms

A folded architecture and a digit-serial architecture are proposed for implementation of one- and two-dimensional discrete wavelet transforms. In the one-dimensional folded architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded architecture is minimized by the use of a generalized life time analysis. The converter units are synthesized with a minimum number of registers using forward-backward allocation. The advantage of the folded architecture is low latency and its drawbacks are increased hardware area, less than 100% hardware utilization, and the complex routing and interconnection required by the converters used. These drawbacks are eliminated in the alternate digit-serial architecture at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, the use of the folded architecture is suggested. If latency is not so critical, the digit-serial architecture should be used. The use of a combined folded and digit-serial architecture is proposed for implementation of two-dimensional discrete wavelet transforms     

一种无乘法高性能9/7离散小波变换滤波器的硬件设计

提出了一种基于提升格式,高效、实时实现JPEG2000中9／7双正交离散小波变换虑波器的VLSI结构设计方法。该方法所设计的结构,在保证同样的精度下,大大减少了运算量,整体运算速度高,硬件花费少,存储需求低,硬件利用率达到100％。用Verilog HDL对系统进行了硬件描述,并选用Xilinx公司的xcv50e-cs144-8器件在ISE4．1环境下实现了综合。     

Efficient hierarchical chaotic image encryption algorithm and itsVLSI realisation

An efficient hierarchical chaotic image encryption algorithm and its VLSI architecture are proposed. Based on a chaotic system and a permutation scheme, all the partitions of the original image are rearranged and the pixels in each partition are scrambled. Its properties of high security, parallel and pipeline processing, and no distortion are analysed. To implement the algorithm, its VLSI architecture with pipeline processing, real-time processing capability, and low hardware cost is designed and the FPGA realisation of its key modules is given. Finally, the encrypted image is simulated and its fractal dimension is computed to demonstrate the effectiveness of the proposed scheme     

A real-time industrial pattern classification system

Using the partitioned matrix approach, a parallel hardware architecture for a parametric (Bayes) classifier is designed. The architecture consists of simple, regularly structured processing elements operating in parallel. As a result, the proposed design is suitable for VLSI implementation. A comparative analysis shows that the approach is more efficient and can significantly reduce the cost required for implementing the classifier, while maintaining high speed     

二维DWT／IDWT处理器的VLSI设计

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统，采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合，综合结果表明：系统的规模为７１４０单元面积，对于四层信小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ。     

An area-efficient very large scale integration architecture for modified Euclidean algorithm with dynamic storage technique

A Modified Euclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties, an area-efficient very large scale integration (VLSI) architecture with dynamic storage technique is proposed to perform the ME algorithm. The dynamic storage technique is used to avoid data exchange and save hardware resources. The proposed architecture with dynamic storage technique can reduce 50% computation hardware area and about 30% memory hardware area. VLSI implementation results of different RS codes show that the proposed architecture is significantly area-efficient, especially for RS codes with long code lengths.     

MARVLE: a VLSI chip for data compression using tree-based codes

Describes the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a memory-based architecture for variable length encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-mm CMOS VLSI chip has been designed, verified, and fabricated by the MOSIS facility. The chip has a 512×12 static RAM with an access time of 4 ns and logic circuitry for compression as well as decompression. The chip occupies a silicon area of 6.8 mm×6.9 mm and consists of 49695 transistors. The prototype chip yields a compression rate of 95.2 Mb/s and a decompression rate of 60.6 Mb/s with a clock rate of 83.3 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.     

An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform

In this brief an efficient folded architecture (EFA) for lifting-based discrete wavelet transform (DWT) is presented. The proposed EFA is based on a novel form of the lifting scheme that is given in this brief. Due to this form, the conventional serial operations of the lifting data flow can be optimized into parallel ones by employing parallel and pipeline techniques. The corresponding optimized architecture (OA) has short critical path latency and is repeatable. Further, utilizing this repeatability, the EFA is derived from the OA by employing the fold technique. For the proposed EFA, hardware utilization achieves 100%, and the number of required registers is reduced. Additionally, the shift-add operation is adopted to optimize the multiplication; thus, the proposed architecture is more suitable for hardware implementation. Performance comparisons and field-programmable gate array (FPGA) implementation results indicate that the proposed EFA possesses better performances in critical path latency, hardware cost, and control complexity.     

Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform

This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.     

Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation

Novel algorithmic features of multimedia applications and advances in VLSI technologies are driving forces behind the new multimedia signal processors. We propose an architecture platform which could provide high performance and flexibility, and would require less external I/O and memory access. It is comprised of array processors to be used as the hardware accelerator and RISC cores to be used as the basis of the programmable processor. It is a hierarchical and scalable architecture style which facilitates the hardware-software codesign of multimedia signal processing circuits and systems. While some control-intensive functions can be implemented using programmable CPUs, other computation-intensive functions can rely on hardware accelerators.To compile multimedia algorithms, we also present an operation placement and scheduling scheme suitable for the proposed architectural platform. Our scheme addresses data reusability and exploits local communication in order to avoid the memory/communication bandwidth bottleneck, which leads to faster program execution. Our method shows a promising performance: a linear speed-up of 16 times can be achieved for the block-matching motion estimation algorithm and the true motion tracking algorithm, which have formed many multimedia applications (e.g., MPEG-2 and MPEG-4).