Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

硅-玻璃静电键合中的电流-时间特性分析

在微传感器和微机械结构的静电键合实验中 ,当加电压到键合片对上时 ,外电路的电流迅速上升到一定值后 ,不是逐渐减小 ,而是较缓慢的继续上升 ,或在某一值停留一段时间再逐渐减小到最小值。通过对实验现象的分析 ,认为键合的电流 -时间特性主要是下述两个过程的综合反映 ,键合过程中接触电阻的减小引起的电流增大和空间电荷区形成引起的电流减小 ,正是由于这两个主要因素导致了上述现象的存在     

低温阳极键合技术研究

通过键合温度220~250℃、键合电压400~600 V的硅玻璃低温阳极键合实验,分析了温度和电场分别对键合强度和键合效率的影响,并讨论了键合机理。     

MEMS硅玻璃阳极键合工艺评价方法

为了得到微机电系统(MEMS)加速度计硅-玻璃阳极键合的键合强度,进行了剪切破坏测试,并结合材料力学相关理论,得到键合强度表征方法.通过对实验数据的分析,制定键合强度的失效判据,提出了一种评价硅玻璃键合工艺质量的有效方法,在工程实际中具有一定的参考价值.     

两电极多层阳极键合实验研究

介绍了用2个电极通过一次电极反接的方式实现多层样片之间阳极键合的操作工艺和键合机理,并以玻璃-硅-玻璃三层结构为例对其进行了实验研究。结果显示：多余的玻璃对第一次键合过程的电流特性影响不大,而第一次键合的玻璃对第二次键合电流产生显著的影响,电流出现不规则的突变。而且,在第二次键合过程中,第一次键合的玻璃在键合面上会出现由于钠元素积聚而产生的黄褐色斑点。拉伸强度实验的结果表明：第二次键合过程中在第一次键合面形成的反向电压会减弱键合的强度;通过合理选择键合参数可以得到满足MEMS封装要求的键合强度。     

采用线阴极的快速阳极键合方法

在平板阴极和点阴极方式做阳极键合时,时间-电流特性、键合速度、结合界面质量等都有所不同。通过建立力学和电学模型,分析了不同阴极形状对阳极键合的时间、强度以及结合界面特性的影响。根据模型分析,采取了线阴极工作方式做阳极键合,样品的键合区扩散时间只需要84s。结合界面无空洞,键合强度为16.7MPa。     

复合量程加速度计阳极键合残余应力研究

复合量程加速度计阳极键合过程中产生的残余热应力会引起加速度计的零位失调,也是导致加速度计失效的原因之一。对键合过程中产生的残余热应力进行了研究,仿真并分析了残余热应力与键合温度、玻璃基底厚度和框架键合宽度的影响,确定了适合复合量程加速度计的最佳键合宽度和玻璃基底厚度。     

阳极键合工艺进展及其在微传感器中的应用

分析了阳极键合技术的原理和当前阳极键合技术的研究进展，综述了微传感器对阳极键合的新需求，展望了阳极键合技术在传感器领域的应用前景。     

On the anodic passivation of silicon in aqueous KOH solutions

This paper proposes a new explanation to account for the anodic passivation of single-crystalline silicon in aqueous KOH. The effects of experimental results.     

Steady-state measurement of wafer bonding cracking resistance

A steady-state wedge-opening test has been developed in order to measure the fracture toughness of bonded silicon wafers. Comparison between non-steady-state and steady-state tests is performed. The importance of allowing the rotation of the testing stage is discussed and appears to be essential in order to have the wedge perfectly aligned with the sample. Significant influence of (1) surface treatment; (2) thermal annealing; and (3) crack velocity on the toughness is observed for Si/Si wafer bonding and related to the interface chemistry.     

A new method for fast anodic bonding in microsystem technology

Other than temperature and voltage, load plays a key role in anodic bonding process. In this paper we present a new design of top electrode (cathode) for anodic bonding machine by which the bonding time has been reduced up to 30 % in case of bare silicon wafer at ?400 V and approximate 52 % in case of oxidized silicon wafer with Pyrex glass bonding at ?800 V. Experimentally it has been observed there was no bonding in oxidized silicon wafer with Pyrex glass up to ?600 V by using standard design while it has been successfully bonded at same voltage (?600 V) by using new design.     

静电键合在高温压力传感器中的应用

分析了硅－玻璃静电键合界面受热循环作用,或者受反向电压作用后,在高温时,键合力的特点,实验验证了高温（４５０℃）时键合面牢固、稳定。研究结果表明高温压力传感器可以采用静电键合技术进行封装。     

静电封接中的热应力研究

通过对静电封接结构的受力分析，建立了静电封接后弹性膜片的热失配应力数学模型。并分析了改善微压传感器性能的技术途径。     

Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides

Plain or structured hydrophillic silicon wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the wafer pairing chosen. If one or both wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the wafer surfaces just prior to bonding are described.     

基于正交试验的光纤传感器金属化连接工艺优化

为了克服光纤传感器有机胶封装带来的可靠性差、应变传递效率低的问题,采用粒子扩散系统对光纤传感器进行金属化连接以实现光纤传感器的无胶封装;为提高金属粘接层与基体的结合强度,设计了以工作距离、驱动电压、进给速度、粒子场气压为试验素的4水平正交试验方案,并用划痕法对金属粘接层的结合强度结果进行评估。通过统计分析,获得了影响金属粘接层与基体结合强度的主要因素和次要因素,优化了光纤传感器金属化连接工艺。     

动车组单车自动校线及耐压试验方法

近些年随着动车组运行功能的不断提升和优化,车辆内部分布的电线电缆数量大量增加,接线测试点在校线、耐压试验环节人工测试付出的时间成本更多。为了避免人工失误影响产品质量,提高测试准确率,提高生产效率,使用自动化测试系统来替代人工试验。本文研制了动车组单车自动校线及耐压试验方法,测试可靠性高并能在不同动车组项目产品之间完成灵活转换,可缩短试验周期,提高测试效率,保障动车组生产的质量。     

Formalizing interoperability for test case generation purpose

This study deals with interoperability testing of protocol implementations. The objective is to define a method for automatic test derivation based on formal definitions. First, the notion of interoperability criteria is introduced. They formally describes the conditions that two implementations must verify in order to be considered interoperable. Then, based on the equivalence of two of the defined interoperability criteria, we propose a method to derive automatically interoperability test cases that avoids the state-space explosion problem.     

Automatic test case generation for structural testing of function block diagrams

ContextFunction Block Diagram (FBD) is increasingly used in safety-critical applications. Test coverage issues for FBDs are frequently raised by regulators and users. However, there is little work at this aspect on testing FBD at model level. Our previous study has designed a new data-flow test coverage criterion, FB-Path Complete Condition Test Coverage (FPCC), that can directly test FBD structures and effectively detect function mutation errors. Nevertheless, because FPCC scheme involves several data-flow concepts and thus it is somewhat complicated to comprehend and to generate FPCC-complied test cases. An automatic test suite generator for FPCC is highly desirable.ObjectiveThis study designs an automatic test case generator, FPCCTestGen, for FPCC so as to enhance the practicability and acceptance of the FPCC approach.MethodFirst, a supporting infrastructure for performing automatic FBD-to-UPPAAL-for-FPCC transformation is designed. The supporting infrastructure includes templates, declarations, and functions as building blocks for transformation. Then, for each input FBD, represented in PLCopen XML format, FPCCTestGen performs parsing and converts FBD components into corresponding UPPAAL model components using aforementioned building blocks. After that, queries related to FPCC characteristics are submitted to UPPAAL model checker for verification. Finally, the verification traces are analyzed to obtain a FPCC-complied test suite.ResultsA safety injection system is used as a case study. Preliminary results show that the generated test suite achieves the highest FPCC percentage with a near optimal number of test cases.ConclusionThis automatic test case generation tool is effective and thus, can promote the use of the new test coverage criterion. Methodology used in FPCCTestGen is generic and can be applied to test suite generation for other test criteria on data-flow programs.     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.